lwn.git/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c, branch docs-mw

phy: mediatek: phy-mtk-hdmi-mt8195: convert from round_rate() to determine_rate()

2025-12-24T07:23:35+00:00

The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Tested-by: Louis-Alexis Eyraud Signed-off-by: Brian Masney Link: https://patch.msgid.link/20251212-phy-clk-round-rate-v3-4-beae3962f767@redhat.com Signed-off-by: Vinod Koul

phy: mediatek: phy-mtk-hdmi: Register PHY provided regulator

2024-12-04T14:25:33+00:00

At least version 2 of the HDMI PHY, found in MediaTek MT8195 and MT8188 SoCs, does provide hardware support to switch on/off the HDMI 5V pins (which are also used for DDC), and this translates to this being a fixed regulator. Register this PHY-provided regulator so that it can be fed to the hdmi-connector driver to manage the HDMI +5V PWR rail. Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20241120124143.132637-1-angelogioacchino.delregno@collabora.com Signed-off-by: Vinod Koul

phy: mediatek: hdmi: mt8195: fix prediv bad upper limit test

2023-07-12T16:57:02+00:00

The pll prediv calculus searchs for the smallest prediv that gets the ns_hdmipll_ck in the range of 5 GHz to 12 GHz. A typo in the upper bound test was testing for 5Ghz to 1Ghz Fixes: 45810d486bb44 ("phy: mediatek: add support for phy-mtk-hdmi-mt8195") Signed-off-by: Guillaume Ranquet Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230529-hdmi_phy_fix-v1-1-bf65f53af533@baylibre.com Signed-off-by: Vinod Koul

phy: mediatek: rework the floating point comparisons to fixed point

2023-05-16T14:18:06+00:00

gcc on aarch64 reports drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c: In function ‘mtk_hdmi_pll_set_rate’: drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c:240:52: error: ‘-mgeneral-regs-only’ is incompatible with the use of floating-point types 240 | else if (tmds_clk >= 54 * MEGA && tmds_clk < 148.35 * MEGA) Floating point should not be used, so rework the floating point comparisons to fixed point. Signed-off-by: Tom Rix Reviewed-by: Chunfeng Yun Link: https://lore.kernel.org/r/20230502145005.2927101-1-trix@redhat.com Signed-off-by: Vinod Koul

phy: mediatek: hdmi: mt8195: fix wrong pll calculus

2023-05-04T17:42:11+00:00

The clock rate calculus in mtk_hdmi_pll_calc() was wrong when it has been replaced by 'div_u64'. Fix the issue by multiplying the values in the denominator instead of dividing them. Fixes: 45810d486bb44 ("phy: mediatek: add support for phy-mtk-hdmi-mt8195") Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Guillaume Ranquet Link: https://lore.kernel.org/r/20230413-fixes-for-mt8195-hdmi-phy-v2-2-bbad62e64321@baylibre.com Signed-off-by: Vinod Koul

phy: mediatek: hdmi: mt8195: fix uninitialized variable usage in pll_calc

2023-05-04T17:42:11+00:00

The ret variable in mtk_hdmi_pll_calc() was used unitialized as reported by the kernel test robot. Fix the issue by removing the variable altogether and testing out the return value of mtk_hdmi_pll_set_hw() Fixes: 45810d486bb44 ("phy: mediatek: add support for phy-mtk-hdmi-mt8195") Reported-by: kernel test robot Signed-off-by: Guillaume Ranquet Reviewed-by: Nathan Chancellor Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230413-fixes-for-mt8195-hdmi-phy-v2-1-bbad62e64321@baylibre.com Signed-off-by: Vinod Koul

phy: mediatek: add support for phy-mtk-hdmi-mt8195

2023-04-12T16:26:41+00:00

Add support for the mediatek hdmi phy on MT8195 SoC Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Guillaume Ranquet Link: https://lore.kernel.org/r/20220919-v8-3-a84c80468fe9@baylibre.com Signed-off-by: Vinod Koul