lwn.git/drivers/net/wireless/ath/wil6210/interrupt.c, branch docs-fixes

wil6210: fix support for sparrow chipsets

2025-06-07T14:36:02+00:00

the wil6210 driver irq handling code is unconditionally writing edma irq registers which are supposed to be only used on Talyn chipsets. This however leade to a chipset hang on the older sparrow chipset generation and firmware will not even boot. Fix that by simply checking for edma support before handling these registers. Tested on Netgear R9000 Signed-off-by: Sebastian Gottschall Link: https://patch.msgid.link/20250304012131.25970-2-s.gottschall@dd-wrt.com Signed-off-by: Jeff Johnson

wil6210: Fix wrong function name in comments

2021-06-15T14:01:25+00:00

Fixes the following W=1 kernel build warning(s): drivers/net/wireless/ath/wil6210/interrupt.c:28: warning: expecting prototype for Theory of operation(). Prototype was for WIL6210_IRQ_DISABLE() instead drivers/net/wireless/ath/wil6210/wmi.c:227: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst drivers/net/wireless/ath/wil6210/wmi.c:245: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst drivers/net/wireless/ath/wil6210/wmi.c:263: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst Cc: Maya Erez Signed-off-by: Yang Shen Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20210517050141.61488-4-shenyang39@huawei.com

wil6210: interrupt: Demote comment header which is clearly not kernel-doc

2020-08-31T15:18:33+00:00

Fixes the following W=1 kernel build warning(s): drivers/net/wireless/ath/wil6210/interrupt.c:652: warning: Function parameter or member 'irq' not described in 'wil6210_thread_irq' drivers/net/wireless/ath/wil6210/interrupt.c:652: warning: Function parameter or member 'cookie' not described in 'wil6210_thread_irq' Cc: Maya Erez Cc: Kalle Valo Cc: "David S. Miller" Cc: Jakub Kicinski Cc: linux-wireless@vger.kernel.org Cc: wil6210@qti.qualcomm.com Cc: netdev@vger.kernel.org Signed-off-by: Lee Jones Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20200827073338.GS3248864@dell

wil6210: add SPDX license identifiers

2019-10-31T08:16:10+00:00

Change all files to add SPDX license identifiers and remove license text. This is only an administrative change, there is no change in actual license or copyright for any file. Signed-off-by: Lior David Signed-off-by: Maya Erez Signed-off-by: Kalle Valo

wil6210: fix missed MISC mbox interrupt

2019-05-03T05:04:36+00:00

When MISC interrupt is triggered due to HALP bit, in parallel to mbox events handling by the MISC threaded IRQ, new mbox interrupt can be missed in the following scenario: 1. MISC ICR is read in the IRQ handler 2. Threaded IRQ is completed and all MISC interrupts are unmasked 3. mbox interrupt is set by FW 4. HALP is masked The mbox interrupt in step 3 can be missed due to constant high level of ICM. Masking all MISC IRQs instead of masking only HALP bit in step 4 will guarantee that ICM will drop to 0 and interrupt will be triggered once MISC interrupts will be unmasked. Signed-off-by: Maya Erez Signed-off-by: Kalle Valo

wil6210: fix spurious interrupts in 3-msi

2019-05-03T05:03:30+00:00

Interrupt is set in ICM (ICR & ~IMV) rising trigger. As the driver masks the IRQ after clearing it, there can be a race where an additional spurious interrupt is triggered when the driver unmask the IRQ. This can happen in case HW triggers an interrupt after the clear and before the mask. To prevent the second spurious interrupt the driver needs to mask the IRQ before reading and clearing it. Signed-off-by: Maya Erez Signed-off-by: Kalle Valo

wil6210: ignore HALP ICR if already handled

2019-02-28T09:24:59+00:00

HALP ICR is set as long as the FW should stay awake. To prevent its multiple handling the driver masks this IRQ bit. However, if there is a different MISC ICR before the driver clears this bit, there is a risk of race condition between HALP mask and unmask. This race leads to HALP timeout, in case it is mistakenly masked. Add an atomic flag to indicate if HALP ICR should be handled. Signed-off-by: Maya Erez Signed-off-by: Kalle Valo

wil6210: add 3-MSI support

2018-07-31T08:00:33+00:00

Extend MSI support to 3-MSI in order to load balance the tx\rx interrupts between different cores. use_msi module parameter has changed to n_msi. Usage: - Set n_msi to 0 for using INTx - Set n_msi to 1 for using single MSI - Set n_msi to 3 for using 3-MSI In 3-MSI configuration MSI 0 is used for TX interrupts, MSI 1 is used for RX interrupts and MSI 2 is used for MISC interrupts. Signed-off-by: Alexei Avshalom Lazar Signed-off-by: Maya Erez Signed-off-by: Kalle Valo

wil6210: add support for enhanced DMA RX data flows

2018-07-02T14:24:38+00:00

Enhanced DMA RX data path is handled using a single RX descriptor ring for all VIFs. Multiple RX status rings are supported, to allow RSS and multi MSI support. The driver gets the RX completions via the RX status rings. The RX status message includes the completed RX buffer ID, which points to the allocated SKB. The enhanced DMA RX data flow supports RX chaining, where multiple SKBs are merged into a single packet. Enhanced DMA HW supports RX HW reorder offload, enabled by default for Talyn-MB. amsdu_en debugfs entry was added to allow control MSDU aggregation. Use the following command to disable AMSDU (enabled by default): echo 0 > amsdu_en Signed-off-by: Gidon Studinski Signed-off-by: Maya Erez Signed-off-by: Kalle Valo

wil6210: add support for enhanced DMA TX data flows

2018-07-02T14:24:29+00:00

The enhanced DMA TX data path is handled using a descriptor ring per connection and a single status ring. The driver gets TX completions via the TX status ring. Each status message points to the completed descriptor ring and includes the number of completed descriptors in this ring. Non TSO enhanced DMA TX descriptors are similar to legacy DMA TX descriptors, hence the same transmit function can be used. However, enhanced DMA TSO frames division is performed by the HW, hence a new function is added to handle enhanced DMA TSO. Signed-off-by: Gidon Studinski Signed-off-by: Maya Erez Signed-off-by: Kalle Valo