<feed xmlns='http://www.w3.org/2005/Atom'>
<title>lwn.git/drivers/net/ethernet/intel/e1000e/ich8lan.c, branch docs-6.1</title>
<subtitle>Linux kernel documentation tree maintained by Jonathan Corbet</subtitle>
<id>http://mirrors.hust.edu.cn/git/lwn.git/atom?h=docs-6.1</id>
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<updated>2022-07-14T16:17:21+00:00</updated>
<entry>
<title>Revert "e1000e: Fix possible HW unit hang after an s0ix exit"</title>
<updated>2022-07-14T16:17:21+00:00</updated>
<author>
<name>Sasha Neftin</name>
<email>sasha.neftin@intel.com</email>
</author>
<published>2022-05-09T08:52:54+00:00</published>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/commit/?id=6cfa45361d3eac31ba67d7d0bbef547151450106'/>
<id>urn:sha1:6cfa45361d3eac31ba67d7d0bbef547151450106</id>
<content type='text'>
This reverts commit 1866aa0d0d6492bc2f8d22d0df49abaccf50cddd.

Commit 1866aa0d0d64 ("e1000e: Fix possible HW unit hang after an s0ix
exit") was a workaround for CSME problem to handle messages comes via H2ME
mailbox. This problem has been fixed by patch "e1000e: Enable the GPT
clock before sending message to the CSME".

Fixes: 3e55d231716e ("e1000e: Add handshake with the CSME to support S0ix")
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=214821
Signed-off-by: Sasha Neftin &lt;sasha.neftin@intel.com&gt;
Tested-by: Naama Meir &lt;naamax.meir@linux.intel.com&gt;
Signed-off-by: Tony Nguyen &lt;anthony.l.nguyen@intel.com&gt;
</content>
</entry>
<entry>
<title>e1000e: Fix possible overflow in LTR decoding</title>
<updated>2022-04-13T16:18:27+00:00</updated>
<author>
<name>Sasha Neftin</name>
<email>sasha.neftin@intel.com</email>
</author>
<published>2022-04-05T15:56:01+00:00</published>
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<id>urn:sha1:04ebaa1cfddae5f240cc7404f009133bb0389a47</id>
<content type='text'>
When we decode the latency and the max_latency, u16 value may not fit
the required size and could lead to the wrong LTR representation.

Scaling is represented as:
scale 0 - 1         (2^(5*0)) = 2^0
scale 1 - 32        (2^(5 *1))= 2^5
scale 2 - 1024      (2^(5 *2)) =2^10
scale 3 - 32768     (2^(5 *3)) =2^15
scale 4 - 1048576   (2^(5 *4)) = 2^20
scale 5 - 33554432  (2^(5 *4)) = 2^25
scale 4 and scale 5 required 20 and 25 bits respectively.
scale 6 reserved.

Replace the u16 type with the u32 type and allow corrected LTR
representation.

Cc: stable@vger.kernel.org
Fixes: 44a13a5d99c7 ("e1000e: Fix the max snoop/no-snoop latency for 10M")
Reported-by: James Hutchinson &lt;jahutchinson99@googlemail.com&gt;
Link: https://bugzilla.kernel.org/show_bug.cgi?id=215689
Suggested-by: Dima Ruinskiy &lt;dima.ruinskiy@intel.com&gt;
Signed-off-by: Sasha Neftin &lt;sasha.neftin@intel.com&gt;
Tested-by: Naama Meir &lt;naamax.meir@linux.intel.com&gt;
Tested-by: James Hutchinson &lt;jahutchinson99@googlemail.com&gt;
Signed-off-by: Tony Nguyen &lt;anthony.l.nguyen@intel.com&gt;
</content>
</entry>
<entry>
<title>e1000e: Correct NVM checksum verification flow</title>
<updated>2022-02-28T21:43:00+00:00</updated>
<author>
<name>Sasha Neftin</name>
<email>sasha.neftin@intel.com</email>
</author>
<published>2022-02-03T12:21:49+00:00</published>
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<id>urn:sha1:ffd24fa2fcc76ecb2e61e7a4ef8588177bcb42a6</id>
<content type='text'>
Update MAC type check e1000_pch_tgp because for e1000_pch_cnp,
NVM checksum update is still possible.
Emit a more detailed warning message.

Bugzilla: https://bugzilla.opensuse.org/show_bug.cgi?id=1191663
Fixes: 4051f68318ca ("e1000e: Do not take care about recovery NVM checksum")
Reported-by: Thomas Bogendoerfer &lt;tbogendoerfer@suse.de&gt;
Signed-off-by: Sasha Neftin &lt;sasha.neftin@intel.com&gt;
Tested-by: Naama Meir &lt;naamax.meir@linux.intel.com&gt;
Signed-off-by: Tony Nguyen &lt;anthony.l.nguyen@intel.com&gt;
</content>
</entry>
<entry>
<title>e1000e: Fix possible HW unit hang after an s0ix exit</title>
<updated>2022-02-28T21:42:28+00:00</updated>
<author>
<name>Sasha Neftin</name>
<email>sasha.neftin@intel.com</email>
</author>
<published>2022-01-25T17:31:23+00:00</published>
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<id>urn:sha1:1866aa0d0d6492bc2f8d22d0df49abaccf50cddd</id>
<content type='text'>
Disable the OEM bit/Gig Disable/restart AN impact and disable the PHY
LAN connected device (LCD) reset during power management flows. This
fixes possible HW unit hangs on the s0ix exit on some corporate ADL
platforms.

Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=214821
Fixes: 3e55d231716e ("e1000e: Add handshake with the CSME to support S0ix")
Suggested-by: Dima Ruinskiy &lt;dima.ruinskiy@intel.com&gt;
Suggested-by: Nir Efrati &lt;nir.efrati@intel.com&gt;
Signed-off-by: Sasha Neftin &lt;sasha.neftin@intel.com&gt;
Tested-by: Kai-Heng Feng &lt;kai.heng.feng@canonical.com&gt;
Signed-off-by: Tony Nguyen &lt;anthony.l.nguyen@intel.com&gt;
</content>
</entry>
<entry>
<title>e1000e: Separate ADP board type from TGP</title>
<updated>2022-02-01T16:59:45+00:00</updated>
<author>
<name>Sasha Neftin</name>
<email>sasha.neftin@intel.com</email>
</author>
<published>2021-12-07T11:23:06+00:00</published>
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<id>urn:sha1:68defd528f94ed1cf11f49a75cc1875dccd781fa</id>
<content type='text'>
We have the same LAN controller on different PCH's. Separate ADP board
type from a TGP which will allow for specific fixes to be applied for
ADP platforms.

Suggested-by: Kai-Heng Feng &lt;kai.heng.feng@canonical.com&gt;
Suggested-by: Dima Ruinskiy &lt;dima.ruinskiy@intel.com&gt;
Signed-off-by: Sasha Neftin &lt;sasha.neftin@intel.com&gt;
Tested-by: Nechama Kraus &lt;nechamax.kraus@linux.intel.com&gt;
Signed-off-by: Tony Nguyen &lt;anthony.l.nguyen@intel.com&gt;
</content>
</entry>
<entry>
<title>e1000e: Fix packet loss on Tiger Lake and later</title>
<updated>2021-10-20T16:06:54+00:00</updated>
<author>
<name>Sasha Neftin</name>
<email>sasha.neftin@intel.com</email>
</author>
<published>2021-09-22T06:55:42+00:00</published>
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<id>urn:sha1:639e298f432fb058a9496ea16863f53b1ce935fe</id>
<content type='text'>
Update the HW MAC initialization flow. Do not gate DMA clock from
the modPHY block. Keeping this clock will prevent dropped packets
sent in burst mode on the Kumeran interface.

Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=213651
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=213377
Fixes: fb776f5d57ee ("e1000e: Add support for Tiger Lake")
Signed-off-by: Sasha Neftin &lt;sasha.neftin@intel.com&gt;
Tested-by: Mark Pearson &lt;markpearson@lenovo.com&gt;
Tested-by: Nechama Kraus &lt;nechamax.kraus@linux.intel.com&gt;
Signed-off-by: Tony Nguyen &lt;anthony.l.nguyen@intel.com&gt;
</content>
</entry>
<entry>
<title>e1000e: Separate TGP board type from SPT</title>
<updated>2021-10-20T15:51:51+00:00</updated>
<author>
<name>Sasha Neftin</name>
<email>sasha.neftin@intel.com</email>
</author>
<published>2021-09-22T06:54:49+00:00</published>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/commit/?id=280db5d420090a24e4e41f9ddcbf37920a598572'/>
<id>urn:sha1:280db5d420090a24e4e41f9ddcbf37920a598572</id>
<content type='text'>
We have the same LAN controller on different PCHs. Separate TGP board
type from SPT which will allow for specific fixes to be applied for
TGP platforms.

Suggested-by: Kai-Heng Feng &lt;kai.heng.feng@canonical.com&gt;
Signed-off-by: Sasha Neftin &lt;sasha.neftin@intel.com&gt;
Reviewed-by: Paul Menzel &lt;pmenzel@molgen.mpg.de&gt;
Tested-by: Mark Pearson &lt;markpearson@lenovo.com&gt;
Tested-by: Nechama Kraus &lt;nechamax.kraus@linux.intel.com&gt;
Signed-off-by: Tony Nguyen &lt;anthony.l.nguyen@intel.com&gt;
</content>
</entry>
<entry>
<title>Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net</title>
<updated>2021-08-27T00:57:57+00:00</updated>
<author>
<name>Jakub Kicinski</name>
<email>kuba@kernel.org</email>
</author>
<published>2021-08-26T20:45:47+00:00</published>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/commit/?id=97c78d0af55fff206947a5f2b85b690b5acf28ce'/>
<id>urn:sha1:97c78d0af55fff206947a5f2b85b690b5acf28ce</id>
<content type='text'>
drivers/net/wwan/mhi_wwan_mbim.c - drop the extra arg.

Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
</content>
</entry>
<entry>
<title>e1000e: Do not take care about recovery NVM checksum</title>
<updated>2021-08-20T15:38:01+00:00</updated>
<author>
<name>Sasha Neftin</name>
<email>sasha.neftin@intel.com</email>
</author>
<published>2021-07-18T04:10:31+00:00</published>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/commit/?id=4051f68318ca9f3d3becef3b54e70ad2c146df97'/>
<id>urn:sha1:4051f68318ca9f3d3becef3b54e70ad2c146df97</id>
<content type='text'>
On new platforms, the NVM is read-only. Attempting to update the NVM
is causing a lockup to occur. Do not attempt to write to the NVM
on platforms where it's not supported.
Emit an error message when the NVM checksum is invalid.

Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=213667
Fixes: fb776f5d57ee ("e1000e: Add support for Tiger Lake")
Suggested-by: Dima Ruinskiy &lt;dima.ruinskiy@intel.com&gt;
Suggested-by: Vitaly Lifshits &lt;vitaly.lifshits@intel.com&gt;
Signed-off-by: Sasha Neftin &lt;sasha.neftin@intel.com&gt;
Tested-by: Dvora Fuxbrumer &lt;dvorax.fuxbrumer@linux.intel.com&gt;
Signed-off-by: Tony Nguyen &lt;anthony.l.nguyen@intel.com&gt;
</content>
</entry>
<entry>
<title>e1000e: Fix the max snoop/no-snoop latency for 10M</title>
<updated>2021-08-20T15:38:01+00:00</updated>
<author>
<name>Sasha Neftin</name>
<email>sasha.neftin@intel.com</email>
</author>
<published>2021-07-04T07:11:41+00:00</published>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/commit/?id=44a13a5d99c71bf9e1676d9e51679daf4d7b3d73'/>
<id>urn:sha1:44a13a5d99c71bf9e1676d9e51679daf4d7b3d73</id>
<content type='text'>
We should decode the latency and the max_latency before directly compare.
The latency should be presented as lat_enc = scale x value:
lat_enc_d = (lat_enc &amp; 0x0x3ff) x (1U &lt;&lt; (5*((max_ltr_enc &amp; 0x1c00)
&gt;&gt; 10)))

Fixes: cf8fb73c23aa ("e1000e: add support for LTR on I217/I218")
Suggested-by: Yee Li &lt;seven.yi.lee@gmail.com&gt;
Signed-off-by: Sasha Neftin &lt;sasha.neftin@intel.com&gt;
Tested-by: Dvora Fuxbrumer &lt;dvorax.fuxbrumer@linux.intel.com&gt;
Signed-off-by: Tony Nguyen &lt;anthony.l.nguyen@intel.com&gt;
</content>
</entry>
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