<feed xmlns='http://www.w3.org/2005/Atom'>
<title>lwn.git/drivers/net/e1000e/ich8lan.c, branch docs-6.1</title>
<subtitle>Linux kernel documentation tree maintained by Jonathan Corbet</subtitle>
<id>http://mirrors.hust.edu.cn/git/lwn.git/atom?h=docs-6.1</id>
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<updated>2011-08-11T03:03:27+00:00</updated>
<entry>
<title>intel: Move the Intel wired LAN drivers</title>
<updated>2011-08-11T03:03:27+00:00</updated>
<author>
<name>Jeff Kirsher</name>
<email>jeffrey.t.kirsher@intel.com</email>
</author>
<published>2011-04-07T14:42:33+00:00</published>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/commit/?id=dee1ad47f2ee75f5146d83ca757c1b7861c34c3b'/>
<id>urn:sha1:dee1ad47f2ee75f5146d83ca757c1b7861c34c3b</id>
<content type='text'>
Moves the Intel wired LAN drivers into drivers/net/ethernet/intel/ and
the necessary Kconfig and Makefile changes.

Signed-off-by: Jeff Kirsher &lt;jeffrey.t.kirsher@intel.com&gt;
</content>
</entry>
<entry>
<title>e1000e: remove unnecessary check for NULL pointer</title>
<updated>2011-08-04T12:00:21+00:00</updated>
<author>
<name>Bruce Allan</name>
<email>bruce.w.allan@intel.com</email>
</author>
<published>2011-07-22T06:21:41+00:00</published>
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<id>urn:sha1:b9e06f70dc186f8353cc593f2b4609383b3be7a9</id>
<content type='text'>
The array shadow_ram is never NULL.

Signed-off-by: Bruce Allan &lt;bruce.w.allan@intel.com&gt;
Tested-by:  Aaron Brown  &lt;aaron.f.brown@intel.com&gt;
Signed-off-by: Jeff Kirsher &lt;jeffrey.t.kirsher@intel.com&gt;
</content>
</entry>
<entry>
<title>intel drivers: repair missing flush operations</title>
<updated>2011-08-04T11:59:07+00:00</updated>
<author>
<name>Jesse Brandeburg</name>
<email>jesse.brandeburg@intel.com</email>
</author>
<published>2011-07-20T00:56:21+00:00</published>
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<id>urn:sha1:945a51517cc0bd9e461f2018624dfc1faef9ddee</id>
<content type='text'>
after review of all intel drivers, found several instances where
drivers had the incorrect pattern of:
memory mapped write();
delay();

which should always be:
memory mapped write();
write flush(); /* aka memory mapped read */
delay();

explanation:
The reason for including the flush is that writes can be held
(posted) in PCI/PCIe bridges, but the read always has to complete
synchronously and therefore has to flush all pending writes to a
device.  If a write is held and followed by a delay, the delay
means nothing because the write may not have reached hardware
(maybe even not until the next read)

Signed-off-by: Jesse Brandeburg &lt;jesse.brandeburg@intel.com&gt;
Tested-by:  Aaron Brown &lt;aaron.f.brown@intel.com&gt;
Signed-off-by: Jeff Kirsher &lt;jeffrey.t.kirsher@intel.com&gt;
</content>
</entry>
<entry>
<title>e1000e: Clear host wakeup bit on 82577/8 without touching PHY page 800</title>
<updated>2011-06-10T03:34:14+00:00</updated>
<author>
<name>Bruce Allan</name>
<email>bruce.w.allan@intel.com</email>
</author>
<published>2011-05-13T07:20:14+00:00</published>
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<id>urn:sha1:3ebfc7c9a6177794e0a1635483bd64268bed5d3c</id>
<content type='text'>
The Host Wakeup Active bit in the PHY Port General Configuration register
(page 769 register 17) must be cleared after every PHY reset to prevent an
unexpected wake signal from the PHY. Originally, this was accomplished by
simply reading the PHY Wakeup Control register on page 800 which clears the
Host Wakeup Active bit as a side-effect. Unfortunately, a hardware bug on
the 82577 and 82578 PHY can cause unexpected behavior when registers on
page 800 are accessed while in gigabit mode.

This patch changes the remaining instances when the Host Wakeup Active bit
needs to be cleared while possibly in gigabit mode by accessing the Port
General Configuration register directly instead of accessing any register
on page 800.

Signed-off-by: Bruce Allan &lt;bruce.w.allan@intel.com&gt;
Tested-by: Jeff Pieper &lt;jeffrey.e.pieper@intel.com&gt;
Signed-off-by: Jeff Kirsher &lt;jeffrey.t.kirsher@intel.com&gt;
</content>
</entry>
<entry>
<title>e1000e: access multiple PHY registers on same page at the same time</title>
<updated>2011-06-10T03:33:36+00:00</updated>
<author>
<name>Bruce Allan</name>
<email>bruce.w.allan@intel.com</email>
</author>
<published>2011-05-13T07:20:09+00:00</published>
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<id>urn:sha1:2b6b168d52aa044363647cfff8bda5cef8068ca3</id>
<content type='text'>
Doing a PHY page select can take a long time, relatively speaking. This
can cause a significant delay when updating a number of PHY registers on
the same page by unnecessarily setting the page for each PHY access. For
example when going to Sx, all the PHY wakeup registers (WUC, RAR[], MTA[],
SHRAR[], IP4AT[], IP6AT[], etc.) on 82577/8/9 need to be updated which
takes a long time which can cause issues when suspending.

This patch introduces new PHY ops function pointers to allow callers to
set the page directly and do any number of PHY accesses on that page.
This feature is currently only implemented for 82577, 82578 and 82579
PHYs for both the normally addressed registers as well as the special-
case addressing of the PHY wakeup registers on page 800. For the latter
registers, the existing function for accessing the wakeup registers has
been divided up into three- 1) enable access to the wakeup register page,
2) perform the register access and 3) disable access to the wakeup register
page. The two functions that enable/disable access to the wakeup register
page are necessarily available to the caller so that the caller can restore
the value of the Port Control (a.k.a. Wakeup Enable) register after the
wakeup register accesses are done.

All instances of writing to multiple PHY registers on the same page are
updated to use this new method and to acquire any PHY locking mechanism
before setting the page and performing the register accesses, and release
the locking mechanism afterward.

Some affiliated magic number cleanup is done as well.

Signed-off-by: Bruce Allan &lt;bruce.w.allan@intel.com&gt;
Tested-by: Jeff Pieper &lt;jeffrey.e.pieper@intel.com&gt;
Signed-off-by: Jeff Kirsher &lt;jeffrey.t.kirsher@intel.com&gt;
</content>
</entry>
<entry>
<title>e1000e: log when swflag is cleared unexpectedly on ICH/PCH devices</title>
<updated>2011-06-10T03:32:28+00:00</updated>
<author>
<name>Bruce Allan</name>
<email>bruce.w.allan@intel.com</email>
</author>
<published>2011-05-13T07:19:53+00:00</published>
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<id>urn:sha1:c5caf4825b22957e4ad70fd94316e91ce8cfb51c</id>
<content type='text'>
Since EXTCNF_CTRL.SWFLAG (used in the ownership arbitration of shared
resources, e.g. the PHY shared between the s/w, f/w, and h/w clients)
can be cleared by any of those clients, log a debug message when
software attempts to clear it and it is already cleared unexpectedly.
And since the swflag is cleared by a hardware reset, the driver does
not need to do that, but the mutex acquired when the bit is set must
still be cleared.

Signed-off-by: Bruce Allan &lt;bruce.w.allan@intel.com&gt;
Tested-by: Aaron Brown &lt;aaron.f.brown@intel.com&gt;
Signed-off-by: Jeff Kirsher &lt;jeffrey.t.kirsher@intel.com&gt;
</content>
</entry>
<entry>
<title>e1000e: 82579 intermittently disabled during S0-&gt;Sx</title>
<updated>2011-06-10T03:31:49+00:00</updated>
<author>
<name>Bruce Allan</name>
<email>bruce.w.allan@intel.com</email>
</author>
<published>2011-05-13T07:19:48+00:00</published>
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<id>urn:sha1:99730e4c13c8344b02dd96108945b48d28c14c25</id>
<content type='text'>
When repeatedly cycling Sx-&gt;S0 states with the network cable unplugged,
the 82579 PHY may not initialize as expected and may require a full power
cycle to recover functionality to the device.  Workaround this by testing
access of the PHY registers after resuming; if that returns unexpected
results toggle the LANPHYPC signal to power cycle the PHY.

This is implemented in the new function e1000_resume_workarounds_pchlan()
which calls another new function, e1000_toggle_lanphypc_value_ich8lan(),
which has been created to reduce code duplication (same functionality
required by a previous workaround).  Also, e1000e_disable_gig_wol_ich8lan
is now e1000_suspend_workarounds_ich8lan to better reflect what it does.

Signed-off-by: Bruce Allan &lt;bruce.w.allan@intel.com&gt;
Tested-by: Aaron Brown &lt;aaron.f.brown@intel.com&gt;
Signed-off-by: Jeff Kirsher &lt;jeffrey.t.kirsher@intel.com&gt;
</content>
</entry>
<entry>
<title>e1000e: implement ethtool set_phys_id</title>
<updated>2011-04-27T09:05:53+00:00</updated>
<author>
<name>Bruce Allan</name>
<email>bruce.w.allan@intel.com</email>
</author>
<published>2011-04-16T00:34:40+00:00</published>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/commit/?id=dbf80dcbd8ca0c50f343401fedd2d6200cb8097e'/>
<id>urn:sha1:dbf80dcbd8ca0c50f343401fedd2d6200cb8097e</id>
<content type='text'>
Based on a patch from Stephen Hemminger &lt;shemminger@vyatta.com&gt;.

The new ethtool set_phys_id takes over controlling the LED for
identifying boards.  This fixes the lockout during that period.
For this device lots of extra infrastructure can also be removed by
using set_phys_id.

v2: - return blink frequency for parts that do not support blink in h/w
    - add blink_led function pointers for devices that do support blink
      in h/w to cleanup the test for this functionality

Signed-off-by: Bruce Allan &lt;bruce.w.allan@intel.com&gt;
Cc: Stephen Hemminger &lt;shemminger@vyatta.com&gt;
Tested-by: Aaron Brown &lt;aaron.f.brown@intel.com&gt;
Signed-off-by: Jeff Kirsher &lt;jeffrey.t.kirsher@intel.com&gt;
</content>
</entry>
<entry>
<title>e1000e: convert short duration msleep() to usleep_range()</title>
<updated>2011-04-14T02:17:06+00:00</updated>
<author>
<name>Bruce Allan</name>
<email>bruce.w.allan@intel.com</email>
</author>
<published>2011-03-19T00:27:20+00:00</published>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/commit/?id=1bba4386ab4f67a53c9649268dd9c83bc6110a9b'/>
<id>urn:sha1:1bba4386ab4f67a53c9649268dd9c83bc6110a9b</id>
<content type='text'>
With durations less than 20ms, the jiffies or legacy timer backed msleep()
may sleep ~20ms which might not be what the caller expects.  Instead, it
is recommended to use the hrtimers backed usleep_range().  For more, see
Documentation/timers/timers-howto.txt.  Issues reported by checkpatch.

In addition, remove unnecessary sleep in e1000e_write_nvm_spi().

Signed-off-by: Bruce Allan &lt;bruce.w.allan@intel.com&gt;
Tested-by: Aaron Brown &lt;aaron.f.brown@intel.com&gt;
Signed-off-by: Jeff Kirsher &lt;jeffrey.t.kirsher@intel.com&gt;
</content>
</entry>
<entry>
<title>e1000e: disable jumbo frames on 82579 when MACsec enabled in EEPROM</title>
<updated>2011-03-11T10:23:21+00:00</updated>
<author>
<name>Bruce Allan</name>
<email>bruce.w.allan@intel.com</email>
</author>
<published>2011-02-25T07:44:51+00:00</published>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/commit/?id=23e4f061306798dfb1941bd2f399949b705822c6'/>
<id>urn:sha1:23e4f061306798dfb1941bd2f399949b705822c6</id>
<content type='text'>
If/when an OEM enables MACsec in the 82579 EEPROM, disable jumbo frames
support in the driver due to an interoperability issue in hardware that
prevents jumbo packets from being transmitted or received.

Signed-off-by: Bruce Allan &lt;bruce.w.allan@intel.com&gt;
Tested-by: Jeff Pieper &lt;jeffrey.e.pieper@intel.com&gt;
Signed-off-by: Jeff Kirsher &lt;jeffrey.t.kirsher@intel.com&gt;
</content>
</entry>
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