lwn.git/drivers/irqchip/irq-armada-370-xp.c, branch v4.3-rc3

irqchip: Kill off set_irq_flags usage

2015-09-16T14:53:38+00:00

set_irq_flags is ARM specific with custom flags which have genirq equivalents. Convert drivers to use the genirq interfaces directly, so we can kill off set_irq_flags. The translation of flags is as follows: IRQF_VALID -> !IRQ_NOREQUEST IRQF_PROBE -> !IRQ_NOPROBE IRQF_NOAUTOEN -> IRQ_NOAUTOEN For IRQs managed by an irqdomain, the irqdomain core code handles clearing and setting IRQ_NOREQUEST already, so there is no need to do this in .map() functions and we can simply remove the set_irq_flags calls. Some users also modify IRQ_NOPROBE and this has been maintained although it is not clear that is really needed. There appears to be a great deal of blind copy and paste of this code. Signed-off-by: Rob Herring Cc: linux-arm-kernel@lists.infradead.org Cc: Russell King Cc: Jason Cooper Cc: Kukjin Kim Cc: Krzysztof Kozlowski Cc: Stephen Warren Cc: Lee Jones Cc: Alexander Shiyan Cc: Maxime Ripard Cc: linux-rpi-kernel@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org Link: http://lkml.kernel.org/r/1440889285-5637-3-git-send-email-robh@kernel.org Signed-off-by: Thomas Gleixner

genirq: Remove irq argument from irq flow handlers

2015-09-16T13:47:51+00:00

Most interrupt flow handlers do not use the irq argument. Those few which use it can retrieve the irq number from the irq descriptor. Remove the argument. Search and replace was done with coccinelle and some extra helper scripts around it. Thanks to Julia for her help! Signed-off-by: Thomas Gleixner Cc: Julia Lawall Cc: Jiang Liu

irqchip: Use irq_desc_get_xxx() to avoid redundant lookup of irq_desc

2015-07-11T21:14:27+00:00

Use irq_desc_get_xxx() to avoid redundant lookup of irq_desc while we already have a pointer to corresponding irq_desc. Signed-off-by: Jiang Liu Cc: Konrad Rzeszutek Wilk Cc: Tony Luck Cc: linux-arm-kernel@lists.infradead.org Cc: Bjorn Helgaas Cc: Benjamin Herrenschmidt Cc: Randy Dunlap Cc: Yinghai Lu Cc: Borislav Petkov Cc: Jason Cooper Cc: Kukjin Kim Cc: Krzysztof Kozlowski Cc: Maxime Ripard Link: http://lkml.kernel.org/r/1433391238-19471-11-git-send-email-jiang.liu@linux.intel.com Signed-off-by: Thomas Gleixner

irqchip: Prepare for local stub header removal

2015-07-11T21:14:23+00:00

The IRQCHIP_DECLARE macro moved to to 'include/linux/irqchip.h', so the local irqchip.h became an empty shell, which solely includes include/linux/irqchip.h Include the global header in all irqchip drivers instead of the local header, so we can remove it. Signed-off-by: Joel Porquet Cc: vgupta@synopsys.com Cc: monstr@monstr.eu Cc: ralf@linux-mips.org Cc: jason@lakedaemon.net Link: http://lkml.kernel.org/r/1882096.X39jVG8e0D@joel-zenbook Signed-off-by: Thomas Gleixner

irqchip: Constify irq_domain_ops

2015-05-05T08:45:58+00:00

The irq_domain_ops are not modified by the driver and the irqdomain core code accepts pointer to a const data. Signed-off-by: Krzysztof Kozlowski Cc: Jason Cooper Cc: Kukjin Kim Cc: Stephen Warren Cc: Lee Jones Cc: Matthias Brugger Cc: Maxime Ripard Cc: linux-arm-kernel@lists.infradead.org Cc: linux-rpi-kernel@lists.infradead.org Cc: linux-mediatek@lists.infradead.org Link: http://lkml.kernel.org/r/1430139264-4362-2-git-send-email-k.kozlowski.k@gmail.com Signed-off-by: Thomas Gleixner

irqchip: armada-370-xp: Allow using wakeup source

2015-04-02T23:00:43+00:00

On the Armada 370/XP SoCs, in standby mode the SoC stay powered and it is possible to wake-up from any interrupt sources. This patch adds flag to the MPIC irqchip driver to let linux know this. Signed-off-by: Gregory CLEMENT Link: https://lkml.kernel.org/r/1427724278-12379-5-git-send-email-gregory.clement@free-electrons.com Signed-off-by: Jason Cooper

irqchip: armada-370-xp: Enable the PMU interrupts

2015-03-08T05:21:57+00:00

In order to let the Performance Monitoring Unit interrupts flowing in the MPIC, we need to unmask these interrupts in the Coherency Fabric Local Interrupt Mask Register. Since this register is a CPU-local register, unmasking this interrupt needs to be done on the boot CPU when the driver initializes, but also on the secondary CPU when they are brought up. Signed-off-by: Maxime Ripard Acked-by: Gregory CLEMENT Link: https://lkml.kernel.org/r/1425379400-4346-4-git-send-email-maxime.ripard@free-electrons.com Signed-off-by: Jason Cooper

irqchip: armada-370-xp: Introduce a is_percpu_irq() helper for readability

2015-03-08T05:21:45+00:00

This commit introduces a helper function is_percpu_irq(), to be used when interrupts are mapped to decide which ones are set as per CPU. This change will allow to extend the list of per cpu interrupts in a less intrusive fashion; also, it makes the code slightly more readable by keeping a list of the per CPU interrupts. Signed-off-by: Ezequiel Garcia Signed-off-by: Maxime Ripard Acked-by: Gregory CLEMENT Link: https://lkml.kernel.org/r/1425379400-4346-3-git-send-email-maxime.ripard@free-electrons.com Signed-off-by: Jason Cooper

irqchip: armada-370-xp: Initialize per cpu registers when CONFIG_SMP=N

2015-03-08T05:21:33+00:00

The irqchip driver called armada_xp_mpic_smp_cpu_init() when CONFIG_SMP=Y to initialize some per cpu registers. The function is called on each CPU by calling it explicitly on the boot CPU and then using a CPU notifier for the non boot CPUs. This commit removes the CONFIG_SMP constrain, so the per cpu registers are also initialized when CONFIG_SMP=N, which is the right thing to do. Signed-off-by: Ezequiel Garcia Signed-off-by: Maxime Ripard Acked-by: Gregory CLEMENT Link: https://lkml.kernel.org/r/1425379400-4346-2-git-send-email-maxime.ripard@free-electrons.com Signed-off-by: Jason Cooper

irqchip: armada-370-xp: Fix chained per-cpu interrupts

2015-03-08T03:58:55+00:00

On the Cortex-A9-based Armada SoCs, the MPIC is not the primary interrupt controller. Yet, it still has to handle some per-cpu interrupt. To do so, it is chained with the GIC using a per-cpu interrupt. However, the current code only call irq_set_chained_handler, which is called and enable that interrupt only on the boot CPU, which means that the parent per-CPU interrupt is never unmasked on the secondary CPUs, preventing the per-CPU interrupt to actually work as expected. This was not seen until now since the only MPIC PPI users were the Marvell timers that were not working, but not used either since the system use the ARM TWD by default, and the ethernet controllers, that are faking there interrupts as SPI, and don't really expect to have interrupts on the secondary cores anyway. Add a CPU notifier that will enable the PPI on the secondary cores when they are brought up. Cc: # 3.15+ Signed-off-by: Maxime Ripard Acked-by: Gregory CLEMENT Link: https://lkml.kernel.org/r/1425378443-28822-1-git-send-email-maxime.ripard@free-electrons.com Signed-off-by: Jason Cooper