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<title>lwn.git/drivers/gpu/drm, branch docs-5.13</title>
<subtitle>Linux kernel documentation tree maintained by Jonathan Corbet</subtitle>
<id>http://mirrors.hust.edu.cn/git/lwn.git/atom?h=docs-5.13</id>
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<updated>2021-03-05T01:13:22+00:00</updated>
<entry>
<title>Merge tag 'amd-drm-fixes-5.12-2021-03-03' of https://gitlab.freedesktop.org/agd5f/linux into drm-fixes</title>
<updated>2021-03-05T01:13:22+00:00</updated>
<author>
<name>Dave Airlie</name>
<email>airlied@redhat.com</email>
</author>
<published>2021-03-05T01:13:21+00:00</published>
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<id>urn:sha1:a1f1054124936c717a64e47862e3d0d820f67a87</id>
<content type='text'>
amd-drm-fixes-5.12-2021-03-03:

amdgpu:
- S0ix fix
- Handle new NV12 SKU
- Misc power fixes
- Display uninitialized value fix
- PCIE debugfs register access fix

Signed-off-by: Dave Airlie &lt;airlied@redhat.com&gt;
From: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20210304043255.3792-1-alexander.deucher@amd.com
</content>
</entry>
<entry>
<title>Merge branch '00.00-inst' of git://github.com/skeggsb/linux into drm-fixes</title>
<updated>2021-03-05T01:10:29+00:00</updated>
<author>
<name>Dave Airlie</name>
<email>airlied@redhat.com</email>
</author>
<published>2021-03-05T00:55:57+00:00</published>
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<id>urn:sha1:a727df407ca4f9bc0e9c30b7b469fc990a235be3</id>
<content type='text'>
A single regression fix here that I noticed while testing a bunch of
boards for something else, not sure where this got lost!  Prevents 3D
driver from initialising on some GPUs.

Signed-off-by: Dave Airlie &lt;airlied@redhat.com&gt;
From: Ben Skeggs &lt;skeggsb@gmail.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/CACAvsv5gmq14BrDmkMncfd=tHVSSaU89BdBEWfs6Jy-aRz03GQ@mail.gmail.com
</content>
</entry>
<entry>
<title>drm/amdgpu: fix parameter error of RREG32_PCIE() in amdgpu_regs_pcie</title>
<updated>2021-03-04T04:05:16+00:00</updated>
<author>
<name>Kevin Wang</name>
<email>kevin1.wang@amd.com</email>
</author>
<published>2021-03-02T07:54:00+00:00</published>
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<id>urn:sha1:1aa46901ee51c1c5779b3b239ea0374a50c6d9ff</id>
<content type='text'>
the register offset isn't needed division by 4 to pass RREG32_PCIE()

Signed-off-by: Kevin Wang &lt;kevin1.wang@amd.com&gt;
Reviewed-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amd/display: fix the return of the uninitialized value in ret</title>
<updated>2021-03-04T04:05:16+00:00</updated>
<author>
<name>Colin Ian King</name>
<email>colin.king@canonical.com</email>
</author>
<published>2021-03-02T14:05:09+00:00</published>
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<id>urn:sha1:b934dd9b44e8ad180b3203ce7d6df3133453ee91</id>
<content type='text'>
Currently if stream-&gt;signal is neither SIGNAL_TYPE_DISPLAY_PORT_MST or
SIGNAL_TYPE_DISPLAY_PORT then variable ret is uninitialized and this is
checked for &gt; 0 at the end of the function.  Ret should be initialized,
I believe setting it to zero is a correct default.

Addresses-Coverity: ("Uninitialized scalar variable")
Fixes: bd0c064c161c ("drm/amd/display: Add return code instead of boolean for future use")
Reviewed-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Colin Ian King &lt;colin.king@canonical.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: enable BACO runpm by default on sienna cichlid and navy flounder</title>
<updated>2021-03-04T04:05:16+00:00</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2021-03-01T15:42:50+00:00</published>
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<id>urn:sha1:25951362db7b3791488ec45bf56c0043f107b94b</id>
<content type='text'>
It works fine and was only disabled because primary GPUs
don't enter runpm if there is a console bound to the fbdev due
to the kmap.  This will at least allow runpm on secondary cards.

Reviewed-by: Evan Quan &lt;evan.quan@amd.com&gt;
Reviewed-by: Rajneesh Bhardwaj &lt;rajneesh.bhardwaj@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/pm: correct Arcturus mmTHM_BACO_CNTL register address</title>
<updated>2021-03-04T04:05:02+00:00</updated>
<author>
<name>Evan Quan</name>
<email>evan.quan@amd.com</email>
</author>
<published>2021-02-19T08:18:47+00:00</published>
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<id>urn:sha1:6efda1671312e8432216ee8b106e71fa3102e1d3</id>
<content type='text'>
Arcturus has a different register address from other SMU V11
ASICs.

Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Acked-by: Guchun Chen &lt;guchun.chen@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amdgpu/swsmu/vangogh: Only use RLCPowerNotify msg for disable</title>
<updated>2021-03-04T03:50:26+00:00</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2021-02-24T20:46:59+00:00</published>
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<id>urn:sha1:992ace410c32955eb5b2cee602ea68ac9557e35b</id>
<content type='text'>
Per discussions with PMFW team, the driver only needs to
notify the PMFW when the RLC is disabled.  The RLC FW will notify
the PMFW directly when it's enabled.

Acked-by: Evan Quan &lt;evan.quan@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/pm: make unsupported power profile messages debug</title>
<updated>2021-03-04T03:49:44+00:00</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2021-02-24T17:21:07+00:00</published>
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<id>urn:sha1:e3746696e78f2185633ae9b47c40fabf88bdcf99</id>
<content type='text'>
Making them an error confuses users and the errors are harmless
as not all asics support all profiles.

Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1488
Acked-by: Nirmoy Das &lt;nirmoy.das@amd.com&gt;
Reviewed-by: Evan Quan &lt;evan.quan@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu:disable VCN for Navi12 SKU</title>
<updated>2021-03-04T03:48:33+00:00</updated>
<author>
<name>Asher.Song</name>
<email>Asher.Song@amd.com</email>
</author>
<published>2021-02-24T10:41:34+00:00</published>
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<id>urn:sha1:0c61ac8134ffc851681ce5d4bd60d97c3d5aed27</id>
<content type='text'>
Navi12 0x7360/C7 SKU has no video support, so remove it.

Reviewed-by: Guchun Chen &lt;guchun.chen@amd.com&gt;
Signed-off-by: Asher.Song &lt;Asher.Song@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amdgpu: Only check for S0ix if AMD_PMC is configured</title>
<updated>2021-03-04T03:46:55+00:00</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2021-02-25T15:21:49+00:00</published>
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<id>urn:sha1:31ada99bdd1b4d6b80462eeb87d383f374409e2a</id>
<content type='text'>
The S0ix check only makes sense if the AMD PMC driver is
present.  We need to use the legacy S3 pathes when the
PMC driver is not present.

Reviewed-by: Prike Liang &lt;Prike.Liang@amd.com&gt;
Reviewed-by: Rajneesh Bhardwaj &lt;rajneesh.bhardwaj@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
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