lwn.git/drivers/gpu/drm/tidss/tidss_dispc.h, branch docs-fixes

drm/tidss: Remove max_pclk_khz and min_pclk_khz from tidss display features

2025-11-12T09:52:40+00:00

The TIDSS hardware does not have independent maximum or minimum pixel clock limits for each video port. Instead, these limits are determined by the SoC's clock architecture. Previously, this constraint was modeled using the 'max_pclk_khz' and 'min_pclk_khz' fields in 'dispc_features', but this approach is static and does not account for the dynamic behavior of PLLs. This patch removes the 'max_pclk_khz' and 'min_pclk_khz' fields from 'dispc_features'. The correct way to check if a requested mode's pixel clock is supported is by using 'clk_round_rate()' in the 'mode_valid()' hook. If the best frequency match for the mode clock falls within the supported tolerance, it is approved. TIDSS supports a 5% pixel clock tolerance, which is now reflected in the validation logic. This change allows existing DSS-compatible drivers to be reused across SoCs that only differ in their pixel clock characteristics. The validation uses 'clk_round_rate()' for each mode, which may introduce additional delay (about 3.5 ms for 30 modes), but this is generally negligible. Users desiring faster validation may bypass these calls selectively, for example, checking only the highest resolution mode, as shown here[1]. [1]: https://lore.kernel.org/all/20250704094851.182131-3-j-choudhary@ti.com/ Tested-by: Michael Walle Reviewed-by: Devarsh Thakkar Reviewed-by: Tomi Valkeinen Signed-off-by: Jayesh Choudhary Signed-off-by: Swamil Jain Link: https://patch.msgid.link/20251104151422.307162-2-s-jain1@ti.com [Tomi: dropped 'inline' from check_pixel_clock] Signed-off-by: Tomi Valkeinen

drm/tidss: Restructure dispc_vp_prepare() and dispc_vp_enable()

2025-10-31T14:56:05+00:00

tidss_crtc.c calls dispc_vp_prepare() and dispc_vp_enable() in that order, next to each other. dispc_vp_prepare() does preparations for enabling the crtc, by writing some registers, and dispc_vp_enable() does more preparations. As the last thing, dispc_vp_enable() enables the CRTC by writing the enable bit. There might have been a reason at some point in the history for this split, but I can't find any point to it. They also do a bit of overlapping work: both call dispc_vp_find_bus_fmt(). They could as well be a single function. But instead of combining them, this patch moves everything from dispc_vp_enable() to dispc_vp_prepare(), except the actual CRTC enable bit write. The reason for this is that unlike all the preparatory register writes, CRTC enable has an immediate effect, starting the timing generator and the CRTC as a whole. Thus it may be important to time the enable just right (as we do in the next patch). No functional changes. Reviewed-by: Devarsh Thakkar Link: https://patch.msgid.link/20250905-tidss-fix-timestamp-v1-1-c2aedf31e2c9@ideasonboard.com Signed-off-by: Tomi Valkeinen

drm/tidss: Fix missing includes and struct decls

2025-08-13T07:20:37+00:00

Fix missing includes and struct declarations. Even if these don't cause any compile issues at the moment, it's good to have them correct. Reviewed-by: Aradhya Bhatia Tested-by: Parth Pancholi Tested-by: Jayesh Choudhary Reviewed-by: Devarsh Thakkar Link: https://lore.kernel.org/r/20250723-cdns-dsi-impro-v5-2-e61cc06074c2@ideasonboard.com Signed-off-by: Tomi Valkeinen

drm/tidss: Add OLDI bridge support

2025-06-26T09:37:24+00:00

The AM62x and AM62Px SoCs feature 2 OLDI TXes each, which makes it possible to connect them in dual-link or cloned single-link OLDI display modes. The current OLDI support in tidss_dispc.c can only support for a single OLDI TX, connected to a VP and doesn't really support configuration of OLDIs in the other modes. The current OLDI support in tidss_dispc.c also works on the principle that the OLDI output can only be served by one, and only one, DSS video-port. This isn't the case in the AM62Px SoC, where there are 2 DSS controllers present that share the OLDI TXes. Having their own devicetree and their own bridge entity will help support the various display modes and sharing possiblilities of the OLDI hardware. For all these reasons, add support for the OLDI TXes as DRM bridges. Signed-off-by: Aradhya Bhatia Signed-off-by: Aradhya Bhatia Tested-by: Michael Walle # on am67a Reviewed-by: Tomi Valkeinen Link: https://lore.kernel.org/r/20250528122544.817829-5-aradhya.bhatia@linux.dev Signed-off-by: Tomi Valkeinen

drm/tidss: Mark AM65x OLDI code separately

2025-06-26T09:37:20+00:00

The dss dt schema and the tidss driver have kept the single-link OLDI in AM65x integrated with the parent video-port (VP) from DSS (as the OLDI configuration happens from the source VP only). To help configure the dual-lvds modes that the OLDI has to offer in devices AM62x and later, a new OLDI bridge driver will be introduced. Mark the existing OLDI code separately by renaming all the current OLDI identifiers with the 'AM65X_' prefix in tidss driver, to help distinguish from the upcoming OLDI bridge driver. Reviewed-by: Tomi Valkeinen Signed-off-by: Aradhya Bhatia Link: https://lore.kernel.org/r/20250528122544.817829-4-aradhya.bhatia@linux.dev Signed-off-by: Tomi Valkeinen

drm/tidss: Add support for AM62L display subsystem

2025-05-20T11:43:56+00:00

Enable display for AM62L DSS [1] which supports only a single display pipeline using a single overlay manager, single video port and a single video lite pipeline which does not support scaling. The output of video port is routed to SoC boundary via DPI interface and the DPI signals from the video port are also routed to DSI Tx controller present within the SoC. [1]: Section 11.7 (Display Subsystem and Peripherals) Link : https://www.ti.com/lit/pdf/sprujb4 Signed-off-by: Devarsh Thakkar Reviewed-by: Tomi Valkeinen Link: https://lore.kernel.org/r/20250507180631.874930-4-devarsht@ti.com Signed-off-by: Tomi Valkeinen

drm/tidss: Update infrastructure to support K3 DSS cut-down versions

2025-05-20T11:43:56+00:00

SoCs like AM62Lx support cut-down version of K3 DSS where although same register space is supported as in other K3 DSS supported SoCs such as AM65x, AM62x, AM62Ax but some of the resources such as planes and corresponding register spaces are truncated. For e.g. AM62Lx has only single VIDL pipeline supported, so corresponding register spaces for other video pipelines need to be skipped. To add a generic support for future SoCs where one or more video pipelines can get truncated from the parent register space, move the video plane related information to vid_info struct which will also have a field to indicate hardware index of each of the available video planes, so that driver only maps and programs those video pipes and skips the unavailable ones. While at it, also change the num_planes field in the features structure to num_vid so that all places in code which use vid_info structure are highlighted in the code. Signed-off-by: Devarsh Thakkar Reviewed-by: Tomi Valkeinen Link: https://lore.kernel.org/r/20250507180631.874930-3-devarsht@ti.com Signed-off-by: Tomi Valkeinen

drm/tidss: Add support for AM62A7 DSS

2023-12-01T10:04:37+00:00

Add support for the DSS controller on TI's AM62A7 SoC in the tidss driver. This controller has 2 video pipelines that can render 2 video planes on over a screen, using the overlay managers. The output of the DSS comes from video port 2 (VP2) in the form of RGB88 DPI signals, while the VP1 is tied off inside the SoC. Also add and use a new type of VP, DISPC_VP_TIED_OFF, for the tied-off VP1 of AM62A DSS. Signed-off-by: Aradhya Bhatia Reviewed-by: Tomi Valkeinen Link: https://lore.kernel.org/r/20231108171619.978438-3-a-bhatia1@ti.com Signed-off-by: Tomi Valkeinen

drm/tidss: Add support for AM625 DSS

2023-06-19T08:30:12+00:00

Add support for the DSS controller on TI's AM625 SoC in the tidss driver. The AM625 DSS supports 2 video planes connecting to 2 video ports. The first plane is a full plane supporting all the features, while the 2nd plane is a "lite" plane without scaling support. The first video port in AM625 DSS internally provides DPI output to 2 OLDI transmitters. Each OLDI TX outputs 4 differential lanes of video output and 1 of clock output. This patch does not automatically enable the OLDI features of AM625 yet. That support for OLDI will be added subsequently. The second video port outputs DPI data directly out of the SoC. It has 24 data lines and can support a maximum of RGB888 output bus format. Signed-off-by: Aradhya Bhatia Reviewed-by: Tomi Valkeinen Signed-off-by: Tomi Valkeinen Link: https://patchwork.freedesktop.org/patch/msgid/20230616150900.6617-3-a-bhatia1@ti.com

drm/tidss: Remove return values from dispc_plane_{setup, enable}()

2023-02-20T14:20:45+00:00

Calls to dispc_plane_setup() and dispc_plane_enable() cannot fail. Remove the return value. Signed-off-by: Thomas Zimmermann Reviewed-by: Javier Martinez Canillas Reviewed-by: Tomi Valkeinen Link: https://patchwork.freedesktop.org/patch/msgid/20230209154107.30680-6-tzimmermann@suse.de