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<title>lwn.git/drivers/gpu/drm/radeon/radeon_display.c, branch next</title>
<subtitle>Linux kernel documentation tree maintained by Jonathan Corbet</subtitle>
<id>http://mirrors.hust.edu.cn/git/lwn.git/atom?h=next</id>
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<updated>2014-05-30T12:13:30+00:00</updated>
<entry>
<title>drm/radeon: lower the ref * post PLL maximum once more</title>
<updated>2014-05-30T12:13:30+00:00</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2014-05-21T13:25:41+00:00</published>
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<id>urn:sha1:4b21ce1b4b5d262e7d4656b8ececc891fc3cb806</id>
<content type='text'>
Let's be conservative and use 100 here until we find something better.

Bugs: https://bugzilla.kernel.org/show_bug.cgi?id=75241

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/radeon: fix typo in finding PLL params</title>
<updated>2014-05-20T12:42:05+00:00</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2014-05-13T10:50:54+00:00</published>
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<id>urn:sha1:74ad54f249de39bc040cce7237b1b854a9c6f0ad</id>
<content type='text'>
Otherwise the limit is raised to high.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Tested-by: Ken Moffat &lt;zarniwhoop@ntlworld.com&gt;
</content>
</entry>
<entry>
<title>drm/radeon: lower the ref * post PLL maximum</title>
<updated>2014-05-06T10:18:44+00:00</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2014-05-01T17:00:41+00:00</published>
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<id>urn:sha1:cbe655137aa8f644f4985021a1e1e65df1d28fa8</id>
<content type='text'>
Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=75241

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/radeon: avoid high jitter with small frac divs</title>
<updated>2014-05-01T10:28:08+00:00</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2014-04-24T16:39:59+00:00</published>
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<id>urn:sha1:3b333c55485fef0089ae7398906599d000df195e</id>
<content type='text'>
Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/radeon: use pflip irq on R600+ v2</title>
<updated>2014-05-01T10:27:42+00:00</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2014-04-23T18:46:06+00:00</published>
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<id>urn:sha1:f5d636d2a74b755879feec35e14a259de52ccc07</id>
<content type='text'>
Testing the update pending bit directly after issuing an
update is nonsense cause depending on the pixel clock the
CRTC needs a bit of time to execute the flip even when we
are in the VBLANK period.

This is just a non invasive patch to solve the problem at
hand, a more complete and cleaner solution should follow
in the next merge window.

Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=76564

v2: fix source IDs for CRTC2-6

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/radeon: improve PLL limit handling in post div calculation</title>
<updated>2014-04-20T15:16:12+00:00</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2014-04-20T11:24:32+00:00</published>
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<id>urn:sha1:c2fb3094669a3205f16a32f4119d0afe40b1a1fd</id>
<content type='text'>
This improves the PLL parameters when we work at
the limits of the allowed ranges.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/radeon: use fixed PPL ref divider if needed</title>
<updated>2014-04-19T16:57:14+00:00</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2014-04-19T16:57:14+00:00</published>
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<id>urn:sha1:24315814239a3fdb306244c99bd076bc79db4ade</id>
<content type='text'>
Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 'drm-next-3.15-wip' of git://people.freedesktop.org/~deathsimple/linux into drm-next</title>
<updated>2014-04-19T01:16:02+00:00</updated>
<author>
<name>Dave Airlie</name>
<email>airlied@gmail.com</email>
</author>
<published>2014-04-19T01:16:02+00:00</published>
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<id>urn:sha1:a42892ed10585c5511e8a3e53f0350b4e2242050</id>
<content type='text'>
Some i2c fixes over DisplayPort.

* 'drm-next-3.15-wip' of git://people.freedesktop.org/~deathsimple/linux:
  drm/radeon: Improve vramlimit module param documentation
  drm/radeon: fix audio pin counts for DCE6+ (v2)
  drm/radeon/dp: switch to the common i2c over aux code
  drm/dp/i2c: Update comments about common i2c over dp assumptions (v3)
  drm/dp/i2c: send bare addresses to properly reset i2c connections (v4)
  drm/radeon/dp: handle zero sized i2c over aux transactions (v2)
  drm/i915: support address only i2c-over-aux transactions
  drm/tegra: dp: Support address-only I2C-over-AUX transactions
</content>
</entry>
<entry>
<title>drm/radeon: improve PLL params if we don't match exactly v2</title>
<updated>2014-04-17T12:14:18+00:00</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2014-04-16T09:54:21+00:00</published>
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<id>urn:sha1:f8a2645ecede4eaf90b3d785f2805c8ecb76d43e</id>
<content type='text'>
Otherwise we might be quite off on older chipsets.

v2: keep ref_div minimum

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/radeon: apply more strict limits for PLL params v2</title>
<updated>2014-04-17T11:59:46+00:00</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2014-04-04T11:45:42+00:00</published>
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<id>urn:sha1:5fb9cc4d8b1639b9a7487c1ee7b2b0c52877327d</id>
<content type='text'>
Letting post and refernce divider get to big is bad for signal stability.

v2: increase the limit to 210

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
</content>
</entry>
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