lwn.git/drivers/gpu/drm/i915/intel_pm.c, branch v4.14-rc4

drm/i915/gen10: implement gen 10 watermarks calculations

2017-08-16T14:42:36+00:00

They're slightly different than the gen 9 calculations. v2: Remove TODO comment. Code matches recent spec. v3: Rebase on top of latest skl code using new fp16.16 and fixing a logic issue. Auto rebase bot has apparently made some bad decisions that changed the logic of the code. (Noticed by Manesh, updated by Rodrigo). Cc: Mahesh Kumar Cc: Maarten Lankhorst Signed-off-by: Paulo Zanoni Signed-off-by: Rodrigo Vivi Reviewed-by: Mahesh Kumar Link: https://patchwork.freedesktop.org/patch/msgid/20170811233825.32083-1-rodrigo.vivi@intel.com

drm/i915/gen10: fix WM latency printing

2017-08-10T20:59:28+00:00

Gen 10 is just like Gen 9, so let's consider that all the future platforms are going to be like gen 9 instead of being like gen8-. Cc: Mahesh Kumar Cc: Maarten Lankhorst Signed-off-by: Paulo Zanoni Signed-off-by: Rodrigo Vivi Reviewed-by: Maarten Lankhorst Link: https://patchwork.freedesktop.org/patch/msgid/20170809205248.11917-4-rodrigo.vivi@intel.com

drm/i915/gen10: fix the gen 10 SAGV block time

2017-08-10T20:59:28+00:00

A previous commit added CNL to intel_has_sagv(), but forgot to adjust the SAGV block time to gen 10 platforms. Cc: Mahesh Kumar Cc: Maarten Lankhorst Signed-off-by: Paulo Zanoni Signed-off-by: Rodrigo Vivi Reviewed-by: Maarten Lankhorst Link: https://patchwork.freedesktop.org/patch/msgid/20170809205248.11917-3-rodrigo.vivi@intel.com

drm/i915/cnl: Enable SAGV for Cannonlake.

2017-08-10T20:59:27+00:00

For now inherit from previous platforms. v2: Rebase on top of CFL. Cc: Mahesh Kumar Cc: Maarten Lankhorst Cc: Paulo Zanoni Signed-off-by: Rodrigo Vivi Reviewed-by: Maarten Lankhorst Link: https://patchwork.freedesktop.org/patch/msgid/20170809205248.11917-2-rodrigo.vivi@intel.com

drm/i915/gen10+: use the SKL code for reading WM latencies

2017-08-10T20:59:27+00:00

Gen 10 should use the exact same code as Gen 9, so change the check to take this into consideration, and also assume that future platforms will run this code. Also add a MISSING_CASE(), just in case we do something wrong, instead of silently failing. Cc: Mahesh Kumar Cc: Maarten Lankhorst Signed-off-by: Paulo Zanoni Signed-off-by: Rodrigo Vivi Reviewed-by: Maarten Lankhorst Link: https://patchwork.freedesktop.org/patch/msgid/20170809205248.11917-1-rodrigo.vivi@intel.com

drm/i915: Add render decompression support

2017-08-10T16:58:36+00:00

SKL+ display engine can scan out certain kinds of compressed surfaces produced by the render engine. This involved telling the display engine the location of the color control surfae (CCS) which describes which parts of the main surface are compressed and which are not. The location of CCS is provided by userspace as just another plane with its own offset. Add the required stuff to validate the user provided AUX plane metadata and convert the user provided linear offset into something the hardware can consume. Due to hardware limitations we require that the main surface and the AUX surface (CCS) be part of the same bo. The hardware also makes life hard by not allowing you to provide separate x/y offsets for the main and AUX surfaces (excpet with NV12), so finding suitable offsets for both requires a bit of work. Assuming we still want keep playing tricks with the offsets. I've just gone with a dumb "search backward for suitable offsets" approach, which is far from optimal, but it works. Also not all planes will be capable of scanning out compressed surfaces, and eg. 90/270 degree rotation is not supported in combination with decompression either. This patch may contain work from at least the following people: * Vandana Kannan * Daniel Vetter * Ben Widawsky v2: Deal with display workarounds 0390, 0531, 1125 (Paulo) v3: Pretend CCS tiles are regular 128 byte wide Y tiles (Jason) Put the AUX register defines to the correct place Fix up the slightly bogus rotation check v4: Use I915_WRITE_FW() due to plane update locking changes s/return -EINVAL/goto err/ in intel_framebuffer_init() Eliminate a bunch hardcoded numbers in CCS code v5: (By Ben) conflict resolution + - res_blocks += fixed_16_16_to_u32_round_up(y_tile_minimum); + res_blocks += fixed16_to_u32_round_up(y_tile_minimum); v6: (daniels) Fix botched commit message. Cc: Paulo Zanoni Cc: Daniel Vetter Cc: Ben Widawsky Cc: Jason Ekstrand Signed-off-by: Ville Syrjä Reviewed-by: Ben Widawsky (v1) Reviewed-by: Daniel Stone Signed-off-by: Ben Widawsky Signed-off-by: Daniel Stone Link: http://patchwork.freedesktop.org/patch/msgid/20170801165817.7063-1-ben@bwidawsk.net

drm/i915: enable WaDisableDopClkGating for skl

2017-08-03T19:30:23+00:00

This WA is required when decoupled frequencies for slice and unslice are enabled. This disables DOP clock gating for skl. v2: enable the WA for all gen9 platforms (not just for SKL GT4 where the hang issue is originally reported) to avoid rare hangs (David) v3: as per WaDatabase, enable it only for SKL (Rodrigo) Cc: David Weinehall Reviewed-by: David Weinehall Signed-off-by: Praveen Paneri Signed-off-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/1501781530-8186-1-git-send-email-praveen.paneri@intel.com

drm/i915: Include mbox details for pcode read/write failures

2017-07-28T10:03:26+00:00

If we fail at punit communication, include both the mbox address and the value we tried to write so that we can identify the invalid sequence. Signed-off-by: Chris Wilson Cc: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20170728085022.1586-1-chris@chris-wilson.co.uk Reviewed-by: Daniel Vetter

drm/i915: Fix bad comparison in skl_compute_plane_wm, v2.

2017-07-19T11:51:58+00:00

ddb_allocation && ddb_allocation / blocks_per_line >= 1 is the same as ddb_allocation >= blocks_per_line, so use the latter to simplify this. This fixes the following compiler warning: drivers/gpu/drm/i915/intel_pm.c:4467]: (warning) Comparison of a boolean expression with an integer other than 0 or 1. Changes since v1: - Rebase, was missing the changes to the macro names. Signed-off-by: Maarten Lankhorst Fixes: d555cb5827d6 ("drm/i915/skl+: use linetime latency if ddb size is not available") Cc: "Mahesh Kumar" Reported-by: David Binderman Cc: David Binderman Cc: # v4.13-rc1+ Link: http://patchwork.freedesktop.org/patch/msgid/20170717120230.2023-1-maarten.lankhorst@linux.intel.com Reviewed-by: Mahesh Kumar

drm/i915/skl+: unify cpp value in WM calculation

2017-07-13T14:39:09+00:00

use same cpp value in different phase of plane WM caluclation. Signed-off-by: Mahesh Kumar Reviewed-by: Maarten Lankhorst Signed-off-by: Maarten Lankhorst Link: http://patchwork.freedesktop.org/patch/msgid/20170705143154.32132-7-mahesh1.kumar@intel.com