<feed xmlns='http://www.w3.org/2005/Atom'>
<title>lwn.git/drivers/gpu/drm/i915/gvt/gvt.h, branch standardize-docs</title>
<subtitle>Linux kernel documentation tree maintained by Jonathan Corbet</subtitle>
<id>http://mirrors.hust.edu.cn/git/lwn.git/atom?h=standardize-docs</id>
<link rel='self' href='http://mirrors.hust.edu.cn/git/lwn.git/atom?h=standardize-docs'/>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/'/>
<updated>2017-06-08T05:59:21+00:00</updated>
<entry>
<title>drm/i915/gvt: Tuning the size of MMIO hash lookup table to 2048</title>
<updated>2017-06-08T05:59:21+00:00</updated>
<author>
<name>Changbin Du</name>
<email>changbin.du@intel.com</email>
</author>
<published>2017-06-06T07:56:14+00:00</published>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/commit/?id=178cd160c6652f57571ba3dc0a9091a1f41d9bc8'/>
<id>urn:sha1:178cd160c6652f57571ba3dc0a9091a1f41d9bc8</id>
<content type='text'>
On Skylake platform, The traced virtual mmio registers are up to 2039.
So tuning the hash table size to improve lookup performance.

Signed-off-by: Changbin Du &lt;changbin.du@intel.com&gt;
Signed-off-by: Zhenyu Wang &lt;zhenyuw@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>drm/i915/gvt: Add helper for tuning MMIO hash table</title>
<updated>2017-06-08T05:59:20+00:00</updated>
<author>
<name>Changbin Du</name>
<email>changbin.du@intel.com</email>
</author>
<published>2017-06-06T07:56:13+00:00</published>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/commit/?id=fbfd76c3746a322a9f33f77b66f85d4f68cabe4a'/>
<id>urn:sha1:fbfd76c3746a322a9f33f77b66f85d4f68cabe4a</id>
<content type='text'>
We count all the tracked virtual MMIO registers, which can help us to
tune the MMIO hash table.

v2: Move num_tracked_mmio into gvt structure.

Signed-off-by: Changbin Du &lt;changbin.du@intel.com&gt;
Signed-off-by: Zhenyu Wang &lt;zhenyuw@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>drm/i915/gvt: Make the MMIO attribute wrappers be inline</title>
<updated>2017-06-08T05:59:20+00:00</updated>
<author>
<name>Changbin Du</name>
<email>changbin.du@intel.com</email>
</author>
<published>2017-06-06T07:56:12+00:00</published>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/commit/?id=5c6d4c676d0ccba2dcd97e47e1f10321da423e7d'/>
<id>urn:sha1:5c6d4c676d0ccba2dcd97e47e1f10321da423e7d</id>
<content type='text'>
Function calls are expensive. I have see obvious overhead call to
these wrappers in perf data, especially from the cmd parser side.
So make these simple wrappers be inline to kill them all.

Signed-off-by: Changbin Du &lt;changbin.du@intel.com&gt;
Signed-off-by: Zhenyu Wang &lt;zhenyuw@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>drm/i915/gvt: Make mmio_attribute as type u8 to save 1.5MB memory</title>
<updated>2017-06-08T05:59:20+00:00</updated>
<author>
<name>Changbin Du</name>
<email>changbin.du@intel.com</email>
</author>
<published>2017-06-06T07:56:11+00:00</published>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/commit/?id=56a78de54964894de2f65c9fa8066d5e9843e1ce'/>
<id>urn:sha1:56a78de54964894de2f65c9fa8066d5e9843e1ce</id>
<content type='text'>
Type u8 is big enough to contain all MMIO attribute flags. As the
total MMIO size is 2MB so we saved 1.5MB memory.

Signed-off-by: Changbin Du &lt;changbin.du@intel.com&gt;
Signed-off-by: Zhenyu Wang &lt;zhenyuw@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>drm/i915/gvt: Add runtime_pm get/put to proctect MMIO accessing</title>
<updated>2017-06-08T05:59:18+00:00</updated>
<author>
<name>Chuanxiao Dong</name>
<email>chuanxiao.dong@intel.com</email>
</author>
<published>2017-06-02T07:34:23+00:00</published>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/commit/?id=9b7bd65ecdf347b33c37d73b610fd85774b12e87'/>
<id>urn:sha1:9b7bd65ecdf347b33c37d73b610fd85774b12e87</id>
<content type='text'>
In some cases, GVT-g is accessing MMIO without holding runtime_pm
and this patch can add the inline API for doing the runtime_pm get/put
to make sure when accessing HW MMIO the i915 HW is really powered on.

Suggested-by: Zhenyu Wang &lt;zhenyuw@linux.intel.com&gt;
Signed-off-by: Chuanxiao Dong &lt;chuanxiao.dong@intel.com&gt;
Cc: Zhenyu Wang &lt;zhenyuw@linux.intel.com&gt;
Signed-off-by: Zhenyu Wang &lt;zhenyuw@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>drm/i915/gvt: Support event based scheduling</title>
<updated>2017-06-08T05:59:16+00:00</updated>
<author>
<name>Ping Gao</name>
<email>ping.a.gao@intel.com</email>
</author>
<published>2017-05-24T12:30:17+00:00</published>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/commit/?id=c713cb2f9b7e1e9ffa8a379cecb13bc6eacd49b6'/>
<id>urn:sha1:c713cb2f9b7e1e9ffa8a379cecb13bc6eacd49b6</id>
<content type='text'>
This patch decouple the time slice calculation and scheduler, let
other event be able to trigger scheduling without impact the
calculation for QoS.

v2: add only one new enum definition.
v3: fix typo.

Signed-off-by: Ping Gao &lt;ping.a.gao@intel.com&gt;
Signed-off-by: Zhenyu Wang &lt;zhenyuw@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>drm/i915/gvt: Change flood gvt dmesg into trace</title>
<updated>2017-06-08T05:59:16+00:00</updated>
<author>
<name>Xiong Zhang</name>
<email>xiong.y.zhang@intel.com</email>
</author>
<published>2017-05-22T21:38:08+00:00</published>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/commit/?id=7fb6a7d65292a524256ed6e2d0e94071b0c53936'/>
<id>urn:sha1:7fb6a7d65292a524256ed6e2d0e94071b0c53936</id>
<content type='text'>
Currently gvt dmesg is so heavy at drm.debug=0x2 that guest and
host almost couldn't run on xengt.

This patch transfer these repeated messages into trace, so dmesg
is light at drm.debug=0x2, and user could get the target message through
trace event and trace filter.

Suggested-by: Zhi Wang &lt;zhi.a.wang@intel.com&gt;
Signed-off-by: Xiong Zhang &lt;xiong.y.zhang@intel.com&gt;
Signed-off-by: Zhenyu Wang &lt;zhenyuw@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>drm/i915/gvt: clean up the unused last_ctx_submit_time of struct intel_vgpu</title>
<updated>2017-06-08T05:59:15+00:00</updated>
<author>
<name>Changbin Du</name>
<email>changbin.du@intel.com</email>
</author>
<published>2017-05-22T09:46:47+00:00</published>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/commit/?id=7b8d57587025dc294094b73f08b389a498fb107f'/>
<id>urn:sha1:7b8d57587025dc294094b73f08b389a498fb107f</id>
<content type='text'>
Clean up it as it is not used now.

Signed-off-by: Changbin Du &lt;changbin.du@intel.com&gt;
Signed-off-by: Zhenyu Wang &lt;zhenyuw@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'v4.11-rc7' into drm-next</title>
<updated>2017-04-19T01:07:14+00:00</updated>
<author>
<name>Dave Airlie</name>
<email>airlied@redhat.com</email>
</author>
<published>2017-04-19T01:07:14+00:00</published>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/commit/?id=856ee92e8602bd86d34388ac08381c5cb3918756'/>
<id>urn:sha1:856ee92e8602bd86d34388ac08381c5cb3918756</id>
<content type='text'>
Backmerge Linux 4.11-rc7 from Linus tree, to fix some
conflicts that were causing problems with the rerere cache
in drm-tip.
</content>
</entry>
<entry>
<title>Merge tag 'gvt-fixes-2017-04-01' of https://github.com/01org/gvt-linux into drm-intel-fixes</title>
<updated>2017-04-03T15:18:34+00:00</updated>
<author>
<name>Jani Nikula</name>
<email>jani.nikula@intel.com</email>
</author>
<published>2017-04-03T15:14:06+00:00</published>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/commit/?id=cf082a4a264d5e0bb79f0055be02d255438836a4'/>
<id>urn:sha1:cf082a4a264d5e0bb79f0055be02d255438836a4</id>
<content type='text'>
gvt-fixes-2017-04-01

- Fix cfg space in failsafe (Changbin)
- Fix a race for irq inject with vgpu release (Zhi)
- Fix golden state firmware load (Zhi)

Link: http://patchwork.freedesktop.org/patch/msgid/20170401080650.6cvqon7nsbziwnyc@zhen-hp.sh.intel.com
Signed-off-by: Jani Nikula &lt;jani.nikula@intel.com&gt;
</content>
</entry>
</feed>
