<feed xmlns='http://www.w3.org/2005/Atom'>
<title>lwn.git/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c, branch master</title>
<subtitle>Linux kernel documentation tree maintained by Jonathan Corbet</subtitle>
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<updated>2022-02-09T21:57:51+00:00</updated>
<entry>
<title>drm/amdkfd: Remove unused old debugger implementation</title>
<updated>2022-02-09T21:57:51+00:00</updated>
<author>
<name>Mukul Joshi</name>
<email>mukul.joshi@amd.com</email>
</author>
<published>2022-02-04T16:58:32+00:00</published>
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<id>urn:sha1:5bdd3eb253544b1e80f904e1205699d0a126d2d6</id>
<content type='text'>
Cleanup the kfd code by removing the unused old debugger
implementation.
The address watch was only ever implemented in the upstream
driver for GFXv7 (Kaveri). The user mode tools runtime using
this API was never open-sourced. Work on the old debugger
prototype that used this API has been discontinued years ago.
Only a small piece of resetting wavefronts is kept and
is moved to kfd_device_queue_manager.c.

Signed-off-by: Mukul Joshi &lt;mukul.joshi@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdkfd: CRIU checkpoint and restore queue control stack</title>
<updated>2022-02-07T22:59:52+00:00</updated>
<author>
<name>David Yat Sin</name>
<email>david.yatsin@amd.com</email>
</author>
<published>2021-01-25T19:09:32+00:00</published>
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<id>urn:sha1:3a9822d7bd623be9000cef8101ecf8479fa53f2c</id>
<content type='text'>
Checkpoint contents of queue control stacks on CRIU dump and restore them
during CRIU restore.

Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: David Yat Sin &lt;david.yatsin@amd.com&gt;
Signed-off-by: Rajneesh Bhardwaj &lt;rajneesh.bhardwaj@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdkfd: CRIU checkpoint and restore queue mqds</title>
<updated>2022-02-07T22:59:52+00:00</updated>
<author>
<name>David Yat Sin</name>
<email>david.yatsin@amd.com</email>
</author>
<published>2021-01-25T17:50:14+00:00</published>
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<id>urn:sha1:42c6c48214b726c30918e8dc80e2168607d13ae4</id>
<content type='text'>
Checkpoint contents of queue MQD's on CRIU dump and restore them during
CRIU restore.

Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: David Yat Sin &lt;david.yatsin@amd.com&gt;
Signed-off-by: Rajneesh Bhardwaj &lt;rajneesh.bhardwaj@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdkfd: CRIU restore queue ids</title>
<updated>2022-02-07T22:59:52+00:00</updated>
<author>
<name>David Yat Sin</name>
<email>david.yatsin@amd.com</email>
</author>
<published>2021-01-25T16:03:31+00:00</published>
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<id>urn:sha1:8668dfc30d3eee695233ce83944abaf5546a5017</id>
<content type='text'>
When re-creating queues during CRIU restore, restore the queue with the
same queue id value used during CRIU dump.

Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Rajneesh Bhardwaj &lt;rajneesh.bhardwaj@amd.com&gt;
Signed-off-by: David Yat Sin &lt;david.yatsin@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdkfd: replace kgd_dev in various kfd2kgd funcs</title>
<updated>2021-11-17T21:58:01+00:00</updated>
<author>
<name>Graham Sider</name>
<email>Graham.Sider@amd.com</email>
</author>
<published>2021-10-14T15:13:33+00:00</published>
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<id>urn:sha1:3356c38dc1b6f74717a9c437b47e9362c8c96ba3</id>
<content type='text'>
Modified definitions:

- program_sh_mem_settings
- set_pasid_vmid_mapping
- init_interrupts
- address_watch_disable
- address_watch_execute
- wave_control_execute
- address_watch_get_offset
- get_atc_vmid_pasid_mapping_info
- set_scratch_backing_va
- set_vm_context_page_table_base
- read_vmid_from_vmfault_reg
- get_cu_occupancy
- program_trap_handler_settings

Signed-off-by: Graham Sider &lt;Graham.Sider@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdkfd: dqm fence memory corruption</title>
<updated>2021-04-01T01:53:25+00:00</updated>
<author>
<name>Qu Huang</name>
<email>jinsdb@126.com</email>
</author>
<published>2021-01-28T12:14:25+00:00</published>
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<id>urn:sha1:e92049ae4548ba09e53eaa9c8f6964b07ea274c9</id>
<content type='text'>
Amdgpu driver uses 4-byte data type as DQM fence memory,
and transmits GPU address of fence memory to microcode
through query status PM4 message. However, query status
PM4 message definition and microcode processing are all
processed according to 8 bytes. Fence memory only allocates
4 bytes of memory, but microcode does write 8 bytes of memory,
so there is a memory corruption.

Changes since v1:
  * Change dqm-&gt;fence_addr as a u64 pointer to fix this issue,
also fix up query_status and amdkfd_fence_wait_timeout function
uses 64 bit fence value to make them consistent.

Signed-off-by: Qu Huang &lt;jinsdb@126.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm, iommu: Change type of pasid to u32</title>
<updated>2020-09-17T17:21:16+00:00</updated>
<author>
<name>Fenghua Yu</name>
<email>fenghua.yu@intel.com</email>
</author>
<published>2020-09-15T16:30:05+00:00</published>
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<id>urn:sha1:c7b6bac9c72c5fcbd6e9e12545bd3022c7f21860</id>
<content type='text'>
PASID is defined as a few different types in iommu including "int",
"u32", and "unsigned int". To be consistent and to match with uapi
definitions, define PASID and its variations (e.g. max PASID) as "u32".
"u32" is also shorter and a little more explicit than "unsigned int".

No PASID type change in uapi although it defines PASID as __u64 in
some places.

Suggested-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Signed-off-by: Fenghua Yu &lt;fenghua.yu@intel.com&gt;
Signed-off-by: Borislav Petkov &lt;bp@suse.de&gt;
Reviewed-by: Tony Luck &lt;tony.luck@intel.com&gt;
Reviewed-by: Lu Baolu &lt;baolu.lu@linux.intel.com&gt;
Acked-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Acked-by: Joerg Roedel &lt;jroedel@suse.de&gt;
Link: https://lkml.kernel.org/r/1600187413-163670-2-git-send-email-fenghua.yu@intel.com
</content>
</entry>
<entry>
<title>drm/amdkfd: Eliminate unnecessary kernel queue function pointers</title>
<updated>2019-12-05T21:24:36+00:00</updated>
<author>
<name>Yong Zhao</name>
<email>Yong.Zhao@amd.com</email>
</author>
<published>2019-11-08T05:30:49+00:00</published>
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<id>urn:sha1:a5a4d68c9326bba7d6ab414a6c1a404f70ab29b1</id>
<content type='text'>
Up to this point, those functions are all the same for all ASICs, so
no need to call them by functions pointers. Removing the function
pointers will greatly increase the code readablity. If there is ever
need for those function pointers, we can add it back then.

Signed-off-by: Yong Zhao &lt;Yong.Zhao@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdkfd: Avoid using doorbell_off as offset in process doorbell pages</title>
<updated>2019-11-13T20:29:45+00:00</updated>
<author>
<name>Yong Zhao</name>
<email>Yong.Zhao@amd.com</email>
</author>
<published>2019-01-15T18:58:57+00:00</published>
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<id>urn:sha1:e47a8b5223033e4dea5e68a228783e3c5ae0b623</id>
<content type='text'>
dorbell_off in the queue properties is mainly used for the doorbell dw
offset in pci bar. We should not set it to the doorbell byte offset in
process doorbell pages. This makes the code much easier to read.

Signed-off-by: Yong Zhao &lt;Yong.Zhao@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdkfd: Eliminate get_atc_vmid_pasid_mapping_valid</title>
<updated>2019-10-03T14:11:04+00:00</updated>
<author>
<name>Yong Zhao</name>
<email>Yong.Zhao@amd.com</email>
</author>
<published>2019-09-26T03:57:30+00:00</published>
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<id>urn:sha1:56fc40aba4d9bc22ccbb8ce88a1c41f666d04f05</id>
<content type='text'>
get_atc_vmid_pasid_mapping_valid() is very similar to
get_atc_vmid_pasid_mapping_pasid(), so they can be merged into a new
function get_atc_vmid_pasid_mapping_info() to reduce register access
times. More importantly, getting the PASID and the valid bit atomically
with a single read fixes some potential race conditions where the
mapping changes between the two reads.

Signed-off-by: Yong Zhao &lt;Yong.Zhao@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
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