<feed xmlns='http://www.w3.org/2005/Atom'>
<title>lwn.git/drivers/gpu/drm/amd/amdgpu/si_dpm.h, branch v6.9</title>
<subtitle>Linux kernel documentation tree maintained by Jonathan Corbet</subtitle>
<id>http://mirrors.hust.edu.cn/git/lwn.git/atom?h=v6.9</id>
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<updated>2020-08-14T20:22:41+00:00</updated>
<entry>
<title>drm/amd/pm: optimize the power related source code layout</title>
<updated>2020-08-14T20:22:41+00:00</updated>
<author>
<name>Evan Quan</name>
<email>evan.quan@amd.com</email>
</author>
<published>2020-08-13T08:39:25+00:00</published>
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<id>urn:sha1:e098bc9612c2b60f94920461d71c92962a916e73</id>
<content type='text'>
The target is to provide a clear entry point(for power routines).
Also this can help to maintain a clear view about the frameworks
used on different ASICs. Hopefully all these can make power part
more friendly to play with.

Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/radeon/dpm: Replace one-element array and use struct_size() helper</title>
<updated>2020-05-28T18:00:50+00:00</updated>
<author>
<name>Gustavo A. R. Silva</name>
<email>gustavoars@kernel.org</email>
</author>
<published>2020-05-22T17:34:19+00:00</published>
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<id>urn:sha1:6e20010a3acc41817daf69f801d8e9c34975223e</id>
<content type='text'>
The current codebase makes use of one-element arrays in the following
form:

struct something {
    int length;
    u8 data[1];
};

struct something *instance;

instance = kmalloc(sizeof(*instance) + size, GFP_KERNEL);
instance-&gt;length = size;
memcpy(instance-&gt;data, source, size);

but the preferred mechanism to declare variable-length types such as
these ones is a flexible array member[1][2], introduced in C99:

struct foo {
        int stuff;
        struct boo array[];
};

By making use of the mechanism above, we will get a compiler warning
in case the flexible array does not occur last in the structure, which
will help us prevent some kind of undefined behavior bugs from being
inadvertently introduced[3] to the codebase from now on. So, replace
the one-element array with a flexible-array member.

Also, make use of the new struct_size() helper to properly calculate the
size of struct NISLANDS_SMC_SWSTATE.

This issue was found with the help of Coccinelle and, audited and fixed
_manually_.

[1] https://gcc.gnu.org/onlinedocs/gcc/Zero-Length.html
[2] https://github.com/KSPP/linux/issues/21
[3] commit 76497732932f ("cxgb3/l2t: Fix undefined behaviour")

Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Gustavo A. R. Silva &lt;gustavoars@kernel.org&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Remove wrapper layer of smu ip functions</title>
<updated>2018-03-15T14:57:50+00:00</updated>
<author>
<name>Rex Zhu</name>
<email>Rex.Zhu@amd.com</email>
</author>
<published>2018-03-12T11:52:23+00:00</published>
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<id>urn:sha1:b905090d2bae2e6189511714a7b88691b439c5a1</id>
<content type='text'>
1. delete amdgpu_powerplay.c used for wrapping smu ip functions
2. delete struct pp_instance,
3. make struct hwmgr as the smu hw handle.

Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Evan Quan &lt;evan.quan@amd.com&gt;
Signed-off-by: Rex Zhu &lt;Rex.Zhu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: unify the interface of amd_pm_funcs</title>
<updated>2017-09-19T03:30:35+00:00</updated>
<author>
<name>Rex Zhu</name>
<email>Rex.Zhu@amd.com</email>
</author>
<published>2017-09-06T10:43:52+00:00</published>
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<id>urn:sha1:cd4d74648b8021f0d0c7cc31a92fb4ea436a0019</id>
<content type='text'>
put amd_pm_funcs table in struct powerplay for all
asics.

Signed-off-by: Rex Zhu &lt;Rex.Zhu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add SI DPM support (v4)</title>
<updated>2016-08-31T19:21:09+00:00</updated>
<author>
<name>Maruthi Bayyavarapu</name>
<email>maruthi.bayyavarapu@amd.com</email>
</author>
<published>2016-08-01T16:42:32+00:00</published>
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<id>urn:sha1:841686df9f7d2942cfd94d024b8591fa3f74ef7c</id>
<content type='text'>
v2: corrected register offset shift
v3: rebase fixes
v4: fix firmware paths
    add SI smc firmware versions for sysfs dump
    remove unused function forward define
    fix the tahiti specific value of DEEP_SLEEP_CLK_SEL field
    fix to miss adding thermal controller
    use vram_type instead of checking mem_gddr5 flag
    fix incorrect index of CG_FFCT_0 register
    fix incorrect reading method at si_get_current_pcie_speed

Signed-off-by: Maruthi Bayyavarapu &lt;maruthi.bayyavarapu@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
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