lwn.git/drivers/gpu/drm/amd/amdgpu/amdgpu.h, branch docs-4.19

drm/amdgpu: add new DF callback for ECC setup

2018-05-24T04:51:21+00:00

The ForceParWrRMW setting needs to be enabled for ECC, but disabled when ECC is not enabled. Reviewed-by: Hawking Zhang Reviewed-by: Junwei Zhang Signed-off-by: Alex Deucher

drm/amdgpu: Enable scatter gather display support

2018-05-15T18:43:49+00:00

Enables sg display if vram size <= THRESHOLD(256M); otherwise still use vram as display buffer. This patch fixed some potention issues introduced by change "allow framebuffer in GART memory as well" due to CZ/ST hardware limitation. v2: Change default setting to auto. v3: Move some logic from amdgpu_display_framebuffer_domains() to pin function, suggested by Christian. v4: Split into several patches. v5: Drop module parameter for now. Signed-off-by: Samuel Li Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amdgpu: use pp_feature member to store the mask

2018-05-15T18:43:40+00:00

Signed-off-by: Huang Rui Reviewed-by: Hawking Zhang Reviewed-by: Alex Deucher Acked-by: Christian König Signed-off-by: Alex Deucher

drm/amdgpu: add save restore list cntl gpm and srm firmware support

2018-05-15T18:43:36+00:00

RLC save/restore list cntl/gpm_mem/srm_mem ucodes are used for CGPG and gfxoff function. Signed-off-by: Huang Rui Acked-by: Alex Deucher Acked-by: Christian König Signed-off-by: Alex Deucher

drm/amdgpu: Reserved vram for smu to save debug info.

2018-05-15T18:43:28+00:00

v2: check reserved vram size before allocate. Reviewed-by: Evan Quan Signed-off-by: Rex Zhu Signed-off-by: Alex Deucher

drm/gpu-sched: fix force APP kill hang(v4)

2018-05-15T18:43:17+00:00

issue: there are VMC page fault occurred if force APP kill during 3dmark test, the cause is in entity_fini we manually signal all those jobs in entity's queue which confuse the sync/dep mechanism: 1)page fault occurred in sdma's clear job which operate on shadow buffer, and shadow buffer's Gart table is cleaned by ttm_bo_release since the fence in its reservation was fake signaled by entity_fini() under the case of SIGKILL received. 2)page fault occurred in gfx' job because during the lifetime of gfx job we manually fake signal all jobs from its entity in entity_fini(), thus the unmapping/clear PTE job depend on those result fence is satisfied and sdma start clearing the PTE and lead to GFX page fault. fix: 1)should at least wait all jobs already scheduled complete in entity_fini() if SIGKILL is the case. 2)if a fence signaled and try to clear some entity's dependency, should set this entity guilty to prevent its job really run since the dependency is fake signaled. v2: splitting drm_sched_entity_fini() into two functions: 1)The first one is does the waiting, removes the entity from the runqueue and returns an error when the process was killed. 2)The second one then goes over the entity, install it as completion signal for the remaining jobs and signals all jobs with an error code. v3: 1)Replace the fini1 and fini2 with better name 2)Call the first part before the VM teardown in amdgpu_driver_postclose_kms() and the second part after the VM teardown 3)Keep the original function drm_sched_entity_fini to refine the code. v4: 1)Rename entity->finished to entity->last_scheduled; 2)Rename drm_sched_entity_fini_job_cb() to drm_sched_entity_kill_jobs_cb(); 3)Pass NULL to drm_sched_entity_fini_job_cb() if -ENOENT; 4)Replace the type of entity->fini_status with "int"; 5)Remove the check about entity->finished. Signed-off-by: Monk Liu Signed-off-by: Emily Deng Reviewed-by: Christian König Signed-off-by: Alex Deucher

drm/amdgpu: add emit_reg_write_reg_wait ring callback

2018-05-15T18:43:13+00:00

This callback writes a value to a register and then reads back another register and waits for a value in a single operation. Provide a helper function using two operations for engines that don't support this opertion. Reviewed-by: Huang Rui Reviewed-by: Christian König Signed-off-by: Alex Deucher

drm/amdgpu/gfx9: cache DB_DEBUG2 and make it available to userspace

2018-05-15T18:43:11+00:00

Userspace needs to query this value to work around a hw bug in certain cases. Acked-by: Nicolai Hähnle Signed-off-by: Alex Deucher

drm/amdgpu: add MP1 and THM hw ip base reg offset

2018-05-15T18:43:04+00:00

Signed-off-by: Evan Quan Reviewed-by: Rex Zhu Signed-off-by: Alex Deucher

drm/amdgpu: add asic need_full_reset callback

2018-04-11T18:07:57+00:00

Allow us to determine at the soc level whether the asic requires full reset or if soft reset will work. Reviewed-by: Christian König Reviewed-by: Huang Rui Signed-off-by: Alex Deucher