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<title>lwn.git/drivers/gpio/gpio-aspeed.c, branch docs-4.14</title>
<subtitle>Linux kernel documentation tree maintained by Jonathan Corbet</subtitle>
<id>http://mirrors.hust.edu.cn/git/lwn.git/atom?h=docs-4.14</id>
<link rel='self' href='http://mirrors.hust.edu.cn/git/lwn.git/atom?h=docs-4.14'/>
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<updated>2017-08-15T09:26:08+00:00</updated>
<entry>
<title>gpio: aspeed: Remove reference to clock name in debounce warning message</title>
<updated>2017-08-15T09:26:08+00:00</updated>
<author>
<name>Andrew Jeffery</name>
<email>andrew@aj.id.au</email>
</author>
<published>2017-08-08T06:07:36+00:00</published>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/commit/?id=754c04582a98fa2a24ff1b4c4b88964b114eb526'/>
<id>urn:sha1:754c04582a98fa2a24ff1b4c4b88964b114eb526</id>
<content type='text'>
HPLL is in fact not the clock we need. Remove the description of which clock we
failed to find a phandle to in order to avoid any further error.

Signed-off-by: Andrew Jeffery &lt;andrew@aj.id.au&gt;
Acked-by: Joel Stanley &lt;joel@jms.id.au&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>gpio: aspeed: Don't attempt to debounce if disabled</title>
<updated>2017-05-22T08:37:07+00:00</updated>
<author>
<name>Joel Stanley</name>
<email>joel@jms.id.au</email>
</author>
<published>2017-05-02T06:08:24+00:00</published>
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<id>urn:sha1:df563c85de690ec0a1c7e49bd1d43ff743dfb1ce</id>
<content type='text'>
We warn the user at driver probe time that debouncing is disabled.
However, if they request debouncing later on we print a confusing error
message:

 gpio_aspeed 1e780000.gpio: Failed to convert 5000us to cycles at 0Hz: -524

Instead bail out when the clock is not present.

Fixes: 5ae4cb94b3133 (gpio: aspeed: Add debounce support)
Signed-off-by: Joel Stanley &lt;joel@jms.id.au&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>gpio: aspeed: Add open-source and open-drain support</title>
<updated>2017-04-24T12:51:57+00:00</updated>
<author>
<name>Andrew Jeffery</name>
<email>andrew@aj.id.au</email>
</author>
<published>2017-04-07T12:59:02+00:00</published>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/commit/?id=c3bafe017c3bd3f68c21637ce4b78963edf56ec5'/>
<id>urn:sha1:c3bafe017c3bd3f68c21637ce4b78963edf56ec5</id>
<content type='text'>
As per the datasheet, manage the IO and value states to implement
open-source/open-drain, but do this by falling back to gpiolib's
emulation.

This commit simply makes the behaviour explicit for clarity, rather than
relying on the implicit return of -ENOTSUPP to trigger the emulation.

Signed-off-by: Andrew Jeffery &lt;andrew@aj.id.au&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>gpio: aspeed: Add debounce support</title>
<updated>2017-04-24T12:49:53+00:00</updated>
<author>
<name>Andrew Jeffery</name>
<email>andrew@aj.id.au</email>
</author>
<published>2017-04-07T12:59:01+00:00</published>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/commit/?id=5ae4cb94b3133d00857bb2909dae779782db40cb'/>
<id>urn:sha1:5ae4cb94b3133d00857bb2909dae779782db40cb</id>
<content type='text'>
Each GPIO in the Aspeed GPIO controller can choose one of four input
debounce states: to disable debouncing for an input, or select from one
of three programmable debounce timer values. Each GPIO in a
four-bank-set is assigned one bit in each of two debounce configuration
registers dedicated to the set, and selects a debounce state by
configuring the two bits to select one of the four options.

The limitation on debounce timer values is managed by mapping offsets
onto a configured timer value and keeping count of the number of users
a timer has. Timer values are configured on a first-come-first-served
basis.

A small twist in the hardware design is that the debounce configuration
register numbering is reversed with respect to the binary representation
of the debounce timer of interest (i.e. debounce register 1 represents
bit 1, and debounce register 2 represents bit 0 of the timer numbering).

Tested on an AST2500EVB with additional inspection under QEMU's
romulus-bmc machine.

Signed-off-by: Andrew Jeffery &lt;andrew@aj.id.au&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>gpio: aspeed: Remove dependence on GPIOF_* macros</title>
<updated>2017-02-04T20:34:55+00:00</updated>
<author>
<name>Andrew Jeffery</name>
<email>andrew@aj.id.au</email>
</author>
<published>2017-02-02T04:28:17+00:00</published>
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<id>urn:sha1:619e96f4bf9d3d79836c324d59803e3f22606a06</id>
<content type='text'>
1736f75d35e47409ad776273133d0f558a4c8253 is a (v2) patch which had
unresolved review comments[1]. Address the comments by removing the use
of macros from the consumer header (this patch represents the diff
between v2 and v3[2]).

[1] https://lkml.org/lkml/2017/1/26/337
[2] https://lkml.org/lkml/2017/1/26/786

Fixes: 1736f75d35e4 ("gpio: aspeed: Add banks Y, Z, AA, AB and AC")
Signed-off-by: Andrew Jeffery &lt;andrew@aj.id.au&gt;
Acked-by: Joel Stanley &lt;joel@jms.id.au&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>gpio: aspeed: Add banks Y, Z, AA, AB and AC</title>
<updated>2017-01-26T13:45:43+00:00</updated>
<author>
<name>Andrew Jeffery</name>
<email>andrew@aj.id.au</email>
</author>
<published>2017-01-24T06:16:46+00:00</published>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/commit/?id=1736f75d35e47409ad776273133d0f558a4c8253'/>
<id>urn:sha1:1736f75d35e47409ad776273133d0f558a4c8253</id>
<content type='text'>
This is less straight-forward than one would hope, as some banks only
have 4 pins rather than 8, others are output only, yet more (W and
X, already supported) are input-only, and in the case of the g4 SoC bank
AC doesn't exist.

Add some structs to describe the varying properties of different banks
and integrate mechanisms to deny requests for unsupported
configurations.

Signed-off-by: Andrew Jeffery &lt;andrew@aj.id.au&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>gpio: aspeed: Make bank names strings</title>
<updated>2017-01-26T13:31:48+00:00</updated>
<author>
<name>Joel Stanley</name>
<email>joel@jms.id.au</email>
</author>
<published>2017-01-23T05:26:06+00:00</published>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/commit/?id=7153f8ef679d5fcb2d9c69a19613399194600f5b'/>
<id>urn:sha1:7153f8ef679d5fcb2d9c69a19613399194600f5b</id>
<content type='text'>
The Aspeed SoCs have more GPIOs than can be represented with A-Z. The
documentation uses two letter names such as AA and AB, so make the names
a three-character array in the bank struct to accommodate this.

Signed-off-by: Joel Stanley &lt;joel@jms.id.au&gt;
Signed-off-by: Andrew Jeffery &lt;andrew@aj.id.au&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>gpio: aspeed: remove redundant return value check</title>
<updated>2016-09-23T13:11:09+00:00</updated>
<author>
<name>Wei Yongjun</name>
<email>weiyongjun1@huawei.com</email>
</author>
<published>2016-09-21T15:07:56+00:00</published>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/commit/?id=83626bbdf5ca31257066b05db5a38c846ae1e19f'/>
<id>urn:sha1:83626bbdf5ca31257066b05db5a38c846ae1e19f</id>
<content type='text'>
Remove unneeded error handling on the result of a call
to platform_get_resource() when the value is passed to
devm_ioremap_resource().

Signed-off-by: Wei Yongjun &lt;weiyongjun1@huawei.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>gpio: aspeed: fix return value check in aspeed_gpio_probe()</title>
<updated>2016-09-15T12:23:40+00:00</updated>
<author>
<name>Wei Yongjun</name>
<email>weiyongjun1@huawei.com</email>
</author>
<published>2016-09-15T01:30:32+00:00</published>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/commit/?id=7f8b96570291def5104cec6f68bae09bd55b691a'/>
<id>urn:sha1:7f8b96570291def5104cec6f68bae09bd55b691a</id>
<content type='text'>
In case of error, the function devm_ioremap_resource() returns ERR_PTR()
and never returns NULL. The NULL test in the return value check should
be replaced with IS_ERR().

Signed-off-by: Wei Yongjun &lt;weiyongjun1@huawei.com&gt;
Acked-by: Joel Stanley &lt;joel@jms.id.au&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>gpio: aspeed: add MODULE_LICENSE()</title>
<updated>2016-09-13T12:00:39+00:00</updated>
<author>
<name>Linus Walleij</name>
<email>linus.walleij@linaro.org</email>
</author>
<published>2016-09-13T11:43:34+00:00</published>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/commit/?id=e50237c7c298f7966f8445efc7119f87d3add484'/>
<id>urn:sha1:e50237c7c298f7966f8445efc7119f87d3add484</id>
<content type='text'>
The build complains about missing MODULE_LICENSE() in
the Aspeed GPIO driver. The license is evident from the
file header, put in "GPL".

Reported-by: Stephen Rothwell &lt;sfr@canb.auug.org.au&gt;
Cc: Alistair Popple &lt;alistair@popple.id.au&gt;
Cc: Jeremy Kerr &lt;jk@ozlabs.org&gt;
Cc: Andrew Jeffery &lt;andrew@aj.id.au&gt;
Acked-by: Joel Stanley &lt;joel@jms.id.au&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
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