<feed xmlns='http://www.w3.org/2005/Atom'>
<title>lwn.git/drivers/dma/omap-dma.c, branch docs-5.3</title>
<subtitle>Linux kernel documentation tree maintained by Jonathan Corbet</subtitle>
<id>http://mirrors.hust.edu.cn/git/lwn.git/atom?h=docs-5.3</id>
<link rel='self' href='http://mirrors.hust.edu.cn/git/lwn.git/atom?h=docs-5.3'/>
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<updated>2018-04-25T09:26:21+00:00</updated>
<entry>
<title>dmaengine: ti: New directory for Texas Instruments DMA drivers</title>
<updated>2018-04-25T09:26:21+00:00</updated>
<author>
<name>Peter Ujfalusi</name>
<email>peter.ujfalusi@ti.com</email>
</author>
<published>2018-04-25T08:45:03+00:00</published>
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<id>urn:sha1:d88b1397c674178e595319fab4a3cd434c915639</id>
<content type='text'>
Collect the Texas Instruments DMA drivers under drivers/dma/ti/

Signed-off-by: Peter Ujfalusi &lt;peter.ujfalusi@ti.com&gt;
Signed-off-by: Vinod Koul &lt;vkoul@kernel.org&gt;
</content>
</entry>
<entry>
<title>dmaengine: omap-dma: Use vchan_terminate_vdesc() instead of desc_free</title>
<updated>2017-12-04T17:03:51+00:00</updated>
<author>
<name>Peter Ujfalusi</name>
<email>peter.ujfalusi@ti.com</email>
</author>
<published>2017-11-14T14:32:05+00:00</published>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/commit/?id=b1faf0f564ffa6c58f7c7c9a9263dc0f7f78e215'/>
<id>urn:sha1:b1faf0f564ffa6c58f7c7c9a9263dc0f7f78e215</id>
<content type='text'>
To avoid race with vchan_complete, use the race free way to terminate
running transfer.

Signed-off-by: Peter Ujfalusi &lt;peter.ujfalusi@ti.com&gt;
Signed-off-by: Vinod Koul &lt;vinod.koul@intel.com&gt;
</content>
</entry>
<entry>
<title>dmaengine: omap-dma: Implement protection for invalid max_burst</title>
<updated>2017-10-12T16:43:48+00:00</updated>
<author>
<name>Peter Ujfalusi</name>
<email>peter.ujfalusi@ti.com</email>
</author>
<published>2017-10-03T08:35:38+00:00</published>
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<id>urn:sha1:05ec62a106a3b358cdc6ac41025b320dc2dbcb3f</id>
<content type='text'>
the device's max_burst to 16777215 (EN is 24bit unsigned value) so
clients can take this into consideration when setting up the transfer.

During slave transfer preparation check if the requested maxburst is valid.

Signed-off-by: Peter Ujfalusi &lt;peter.ujfalusi@ti.com&gt;
Cc: Russell King &lt;linux@armlinux.org.uk&gt;
Signed-off-by: Vinod Koul &lt;vinod.koul@intel.com&gt;
</content>
</entry>
<entry>
<title>dmaengine: omap-dma: port_window support correction for both direction</title>
<updated>2017-06-20T03:45:01+00:00</updated>
<author>
<name>Peter Ujfalusi</name>
<email>peter.ujfalusi@ti.com</email>
</author>
<published>2017-06-16T15:40:55+00:00</published>
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<id>urn:sha1:9816c09e2c889dfc962f142805eb03fba32debb3</id>
<content type='text'>
When the port_window support was verified it was done on setup where only
the MEM_TO_DEV direction was enabled. This got un-noticed and thus only
this direction worked.

Now that I have managed to get a setup to verify both direction it turned
out that the setup was incorrect:
omap_desc members are settings for the slave port while the omap_sg members
apply to the memory side of the sDMA setup.

Fixes: 527a27591312 ("dmaengine: omap-dma: Fix the port_window support")
Signed-off-by: Peter Ujfalusi &lt;peter.ujfalusi@ti.com&gt;
Cc: Russell King &lt;linux@armlinux.org.uk&gt;
Cc: dmaengine@vger.kernel.org
Cc: dan.j.williams@intel.com
Cc: vinod.koul@intel.com
Tested-by: Tony Lindgren &lt;tony@atomide.com&gt;
Acked-by: Vinod Koul &lt;vinod.koul@intel.com&gt;
Signed-off-by: Bin Liu &lt;b-liu@ti.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>dmaengine: omap-dma: Fix the port_window support</title>
<updated>2017-01-10T05:38:01+00:00</updated>
<author>
<name>Peter Ujfalusi</name>
<email>peter.ujfalusi@ti.com</email>
</author>
<published>2017-01-09T14:50:52+00:00</published>
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<id>urn:sha1:527a27591312e4b3a0f8179f321f9e85c0850df0</id>
<content type='text'>
We do not yet have users of port_window. The following errors were found
when converting the tusb6010_omap.c musb driver:

- The peripheral side must have SRC_/DST_PACKED disabled
- when configuring the burst for the peripheral side the memory side
  configuration were overwritten: d-&gt;csdp = ... -&gt; d-&gt;csdp |= ...
- The EI and FI were configured for the wrong sides of the transfers.

With these changes and the converted tus6010_omap.c I was able to verify
that things are working as they expected to work.

Fixes: 201ac4861c19 ("dmaengine: omap-dma: Support for slave devices with data port window")
Signed-off-by: Peter Ujfalusi &lt;peter.ujfalusi@ti.com&gt;
Signed-off-by: Vinod Koul &lt;vinod.koul@intel.com&gt;
</content>
</entry>
<entry>
<title>dmaengine: omap-dma: Fix dynamic lch_map allocation</title>
<updated>2017-01-03T03:40:15+00:00</updated>
<author>
<name>Peter Ujfalusi</name>
<email>peter.ujfalusi@ti.com</email>
</author>
<published>2017-01-02T10:07:37+00:00</published>
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<id>urn:sha1:836c3ce2566fb8c1754f8d7c9534cad9bc8a6879</id>
<content type='text'>
The original patch did not done what it was supposed to be doing and even
worst it broke legacy boot (OMAP1).

The lch_map size should be the number of available logical channels in sDMA
and the od-&gt;dma_requests should store the number of available DMA request
lines usable in sDMA.

In legacy mode we do not have a way to get the DMA request count, in that
case we use OMAP_SDMA_REQUESTS (127), despite the fact that OMAP1510 have
only 31 DMA request line.

Fixes: 2d1a9a946fae ("dmaengine: omap-dma: Dynamically allocate memory for lch_map")
Reported-by: Aaro Koskinen &lt;aaro.koskinen@iki.fi&gt;
Cc: stable@vger.kernel.org   # v4.9
Signed-off-by: Peter Ujfalusi &lt;peter.ujfalusi@ti.com&gt;
Tested-by: Aaro Koskinen &lt;aaro.koskinen@iki.fi&gt;
Signed-off-by: Vinod Koul &lt;vinod.koul@intel.com&gt;
</content>
</entry>
<entry>
<title>dmaengine: omap-dma: Support for slave devices with data port window</title>
<updated>2016-11-30T03:24:04+00:00</updated>
<author>
<name>Peter Ujfalusi</name>
<email>peter.ujfalusi@ti.com</email>
</author>
<published>2016-11-29T14:23:42+00:00</published>
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<id>urn:sha1:201ac4861c1944ec3794364d6898b4ddfeb0faf8</id>
<content type='text'>
Based on the src/dst_port_window_size - if it is set - configure the DMA
channel to use double indexing in order to be able to loop within the
address window.

Signed-off-by: Peter Ujfalusi &lt;peter.ujfalusi@ti.com&gt;
Signed-off-by: Vinod Koul &lt;vinod.koul@intel.com&gt;
</content>
</entry>
<entry>
<title>dmaengine: omap-dma: initialize can_pause to false</title>
<updated>2016-10-19T13:17:29+00:00</updated>
<author>
<name>Colin Ian King</name>
<email>colin.king@canonical.com</email>
</author>
<published>2016-10-19T11:05:53+00:00</published>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/commit/?id=0741b819246029a7e53b8edcc5693debd7c00c8f'/>
<id>urn:sha1:0741b819246029a7e53b8edcc5693debd7c00c8f</id>
<content type='text'>
can_pause is not initialized so it contains garbage.  Fix this
by setting it to false.

Found using static analysis with cppcheck.

Signed-off-by: Colin Ian King &lt;colin.king@canonical.com&gt;
Signed-off-by: Vinod Koul &lt;vinod.koul@intel.com&gt;
</content>
</entry>
<entry>
<title>dmaengine: omap-dma: add support for pause of non-cyclic transfers</title>
<updated>2016-10-18T14:52:01+00:00</updated>
<author>
<name>Sebastian Andrzej Siewior</name>
<email>bigeasy@linutronix.de</email>
</author>
<published>2016-10-14T05:00:47+00:00</published>
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<id>urn:sha1:9934075471dcc6de9bdce1f3c1e16f1afbd711a8</id>
<content type='text'>
This DMA driver is used by 8250-omap on DRA7-evm. There is one
requirement that is to pause a transfer. This is currently used on the RX
side. It is possible that the UART HW aborted the RX (UART's RX-timeout)
but the DMA controller starts the transfer shortly after.
Before we can manually purge the FIFO we need to pause the transfer,
check how many bytes it already received and terminate the transfer
without it making any progress.

From testing on the TX side it seems that it is possible that we invoke
pause once the transfer has completed which is indicated by the missing
CCR_ENABLE bit but before the interrupt has been noticed. In that case the
interrupt will come even after disabling it.

The AM572x manual says that we have to wait for the CCR_RD_ACTIVE &amp;
CCR_WR_ACTIVE bits to be gone before programming it again here is the
drain loop. Also it looks like without the drain the TX-transfer makes
sometimes progress.

One note: The pause + resume combo is broken because after resume the
the complete transfer will be programmed again. That means the already
transferred bytes (until the pause event) will be sent again. This is
currently not important for my UART user because it does only pause +
terminate.

v3…v4:
 - update subject line.

v2…v3:
  - rephrase the comment based on Russell's information / feedback.

v1…v2:
  - move the drain loop into omap_dma_drain_chan() instead of having it
    twice.
  - allow pause only for DMA_DEV_TO_MEM transfers if non-cyclic. Add a
    comment why DMA_MEM_TO_DEV not allowed.
  - clear pause on terminate_all. Otherwise pause() + terminate_all()
    will keep the pause bit set and we can't pause the following
    transfer.

Signed-off-by: Sebastian Andrzej Siewior &lt;bigeasy@linutronix.de&gt;
[vigneshr@ti.com: drain channel only when buffering is on, rebase to v4.8]
Signed-off-by: Vignesh R &lt;vigneshr@ti.com&gt;
Acked-by: Peter Ujfalusi &lt;peter.ujfalusi@ti.com&gt;
Signed-off-by: Vinod Koul &lt;vinod.koul@intel.com&gt;
</content>
</entry>
<entry>
<title>dmaengine: omap-dma: Enable burst and data pack for SG</title>
<updated>2016-10-01T06:05:27+00:00</updated>
<author>
<name>Misael Lopez Cruz</name>
<email>misael.lopez@ti.com</email>
</author>
<published>2016-09-16T10:53:15+00:00</published>
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<id>urn:sha1:e7b2acfc79f052d023bf15bb6f82c90166ba74b5</id>
<content type='text'>
Enable the burst and data pack modes for the scatter-gather
in order to improve the throughput of the data transfers.

The improvement has been verified with MMC HS200 mode in
the DRA72 EVM using the iozone tool to compare the read
throughput (in kB/s) with and without burst/pack for
different reclens (in kB).

                              With
    reclen    Baseline   sDMA burst/pack
    ------    --------   ---------------
       64       46568         50820
      128       57564         63413
      256       65634         74937
      512       72427         83483
     1024       74563         84504
     2048       76265         86079
     4096       78045         87335
     8192       78989         88154
    16384       81265         91034

Signed-off-by: Misael Lopez Cruz &lt;misael.lopez@ti.com&gt;
Signed-off-by: Peter Ujfalusi &lt;peter.ujfalusi@ti.com&gt;
Signed-off-by: Vinod Koul &lt;vinod.koul@intel.com&gt;
</content>
</entry>
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