lwn.git/drivers/clk/socfpga/clk-pll-s10.c, branch docs-fixes

Convert 'alloc_obj' family to use the new default GFP_KERNEL argument

2026-02-22T01:09:51+00:00

This was done entirely with mindless brute force, using git grep -l '\

treewide: Replace kmalloc with kmalloc_obj for non-scalar types

2026-02-21T09:02:28+00:00

This is the result of running the Coccinelle script from scripts/coccinelle/api/kmalloc_objs.cocci. The script is designed to avoid scalar types (which need careful case-by-case checking), and instead replace kmalloc-family calls that allocate struct or union object instances: Single allocations: kmalloc(sizeof(TYPE), ...) are replaced with: kmalloc_obj(TYPE, ...) Array allocations: kmalloc_array(COUNT, sizeof(TYPE), ...) are replaced with: kmalloc_objs(TYPE, COUNT, ...) Flex array allocations: kmalloc(struct_size(PTR, FAM, COUNT), ...) are replaced with: kmalloc_flex(*PTR, FAM, COUNT, ...) (where TYPE may also be *VAR) The resulting allocations no longer return "void *", instead returning "TYPE *". Signed-off-by: Kees Cook

clk: socfpga: agilex5: add clock driver for Agilex5

2025-10-23T03:52:58+00:00

Add the new Clock manager driver to support new Agilex5 platform. The new driver got rid of the clk_parent_data structures as there are no 'clock-names' property in the DT bindings and use parent_names internally. This is based on the previous feedback from the maintainer. Signed-off-by: Ang Tien Sung Signed-off-by: Khairul Anuar Romli Signed-off-by: Dinh Nguyen

clk: socfpga: stratix10: Optimize local variables

2025-04-24T22:38:07+00:00

Since readl() returns a u32, the local variable reg can also have the data type u32. Furthermore, mdiv and refdiv are derived from reg and can also be a u32. Since do_div() casts the divisor to u32 anyway, changing the data type of refdiv to u32 removes the following Coccinelle/coccicheck warning reported by do_div.cocci: WARNING: do_div() does a 64-by-32 division, please consider using div64_ul instead Compile-tested only. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Thorsten Blum Signed-off-by: Dinh Nguyen

clk: socfpga: cleanup spdx tags

2022-03-12T02:21:45+00:00

Replace tabs with spaces in SPDX tag Signed-off-by: Tom Rix Link: https://lore.kernel.org/r/20220217173453.3262672-1-trix@redhat.com Acked-by: Dinh Nguyen Signed-off-by: Stephen Boyd

clk: socfpga: remove redundant assignment on division

2022-01-06T00:32:43+00:00

The variable parent_rate is being divided by div and the result is re-assigned to parent_rate before being returned. The assignment is redundant, replace /= operator with just / operator. Signed-off-by: Colin Ian King Link: https://lore.kernel.org/r/20211221003750.212780-1-colin.i.king@gmail.com Acked-by: Dinh Nguyen Signed-off-by: Stephen Boyd

clk: socfpga: remove redundant initialization of variable div

2021-04-07T23:30:23+00:00

The variable div is being initialized with a value that is never read and it is being updated later with a new value. The initialization is redundant and can be removed. Addresses-Coverity: ("Unused value") Signed-off-by: Colin Ian King Link: https://lore.kernel.org/r/20210406182746.432861-1-colin.king@canonical.com Acked-by: Dinh Nguyen Signed-off-by: Stephen Boyd

clk: socfpga: Convert to s10/agilex/n5x to use clk_hw

2021-03-31T02:26:26+00:00

As recommended by Stephen Boyd, convert the Agilex/Stratix10/n5x clock driver to use the clk_hw registration method. Suggested-by: Stephen Boyd Signed-off-by: Dinh Nguyen Link: https://lore.kernel.org/r/20210302214151.1333447-3-dinguyen@kernel.org Signed-off-by: Stephen Boyd

clk: socfpga: agilex: add clock driver for eASIC N5X platform

2021-02-12T21:04:58+00:00

Add support for Intel's eASIC N5X platform. The clock manager driver for the N5X is very similar to the Agilex platform, we can re-use most of the Agilex clock driver. This patch makes the necessary changes for the driver to differentiate between the Agilex and the N5X platforms. Signed-off-by: Dinh Nguyen Link: https://lore.kernel.org/r/20210212143059.478554-2-dinguyen@kernel.org Signed-off-by: Stephen Boyd

clk: socfpga: agilex: add clock driver for the Agilex platform

2020-05-27T02:13:05+00:00

For the most part the Agilex clock structure is very similar to Stratix10, so we re-use most of the Stratix10 clock driver. Signed-off-by: Dinh Nguyen Link: https://lkml.kernel.org/r/20200512181647.5071-5-dinguyen@kernel.org Signed-off-by: Stephen Boyd