lwn.git/drivers/clk/mvebu/ap806-system-controller.c, branch docs-fixes

clk: mvebu: ap80x: add AP807 clock support

2019-09-18T05:15:41+00:00

Add driver support for AP807 clock. Signed-off-by: Ben Peled Signed-off-by: Miquel Raynal Link: https://lkml.kernel.org/r/20190805100310.29048-9-miquel.raynal@bootlin.com Signed-off-by: Stephen Boyd

clk: mvebu: ap806: Prepare the introduction of AP807 clock support

2019-09-18T05:15:41+00:00

Factor out the code that is only useful to AP806 so it will be easier to support AP807. No functional changes. Signed-off-by: Ben Peled Signed-off-by: Miquel Raynal Link: https://lkml.kernel.org/r/20190805100310.29048-8-miquel.raynal@bootlin.com Signed-off-by: Stephen Boyd

clk: mvebu: ap806: add AP-DCLK (hclk) to system controller driver

2019-09-18T05:15:41+00:00

Add dynamic AP-DCLK clock (hclk) to system controller driver. AP-DCLK is half the rate of DDR clock, so its derrived from Sample At Reset configuration. The clock frequency is required for AP806 AXI monitor profiling feature. Signed-off-by: Omri Itach Signed-off-by: Miquel Raynal Link: https://lkml.kernel.org/r/20190805100310.29048-7-miquel.raynal@bootlin.com Signed-off-by: Stephen Boyd

clk: mvebu: ap806: be more explicit on what SaR is

2019-09-18T05:15:41+00:00

"SaR" means Sample at Reset. DIP switches can be changed on the board, their states at reset time is available through a register read. Signed-off-by: Miquel Raynal Link: https://lkml.kernel.org/r/20190805100310.29048-6-miquel.raynal@bootlin.com Signed-off-by: Stephen Boyd

clk: mvebu: ap806: Fix clock name for the cluster

2019-08-08T16:08:09+00:00

Actually, the clocks exposed for the cluster are not the CPU clocks, but the PLL clock used as entry clock for the CPU clocks. The CPU clock will be managed by a driver submitting in the following patches. Signed-off-by: Gregory CLEMENT Link: https://lkml.kernel.org/r/20190710134346.30239-5-gregory.clement@bootlin.com Signed-off-by: Stephen Boyd

clk: mvebu: add helper file for Armada AP and CP clocks

2019-08-08T16:08:09+00:00

Clock drivers for Armada AP and Armada CP use the same function to generate unique clock name. A third drivers is coming with the same need, so it's time to move this function in a common file. Signed-off-by: Gregory CLEMENT Link: https://lkml.kernel.org/r/20190710134346.30239-3-gregory.clement@bootlin.com Signed-off-by: Stephen Boyd

Merge branches 'clk-mvebu-periph-pm', 'clk-meson', 'clk-allwinner', 'clk-mvebu-dup' and 'clk-davinci' into clk-next

2018-10-18T22:39:08+00:00

- S2RAM support for Marvell mvebu periph clks * clk-mvebu-periph-pm: clk: mvebu: armada-37xx-periph: add suspend/resume support clk: mvebu: armada-37xx-periph: save the IP base address in the driver data * clk-meson: clk: meson: meson8b: use the regmap in the internal reset controller clk: meson: meson8b: register the clock controller early clk: meson-axg: pcie: drop the mpll3 clock parent clk: meson: axg: round audio system master clocks down clk: meson: clk-pll: drop hard-coded rates from pll tables clk: meson: clk-pll: remove od parameters clk: meson: clk-pll: drop CLK_GET_RATE_NOCACHE where unnecessary clk: meson: clk-pll: add enable bit * clk-allwinner: dt-bindings: clock: sun50i-a64-ccu: Add PLL_VIDEO0 macro clk: sunxi-ng: a64: Add max. rate constraint to video PLLs clk: sunxi-ng: a64: Add minimal rate for video PLLs clk: sunxi-ng: sun50i: h6: Add 2x fixed post-divider to MMC module clocks clk: sunxi-ng: a83t: Add max. rate constraint to video PLLs clk: sunxi-ng: nkmp: Add constraint for maximum rate clk: sunxi-ng: r40: Add max. rate constraint to video PLLs clk: sunxi-ng: h3/h5: Add max. rate constraint to pll-video clk: sunxi-ng: Add maximum rate constraint to NM PLLs clk: sunxi-ng: h6: fix PWM gate/reset offset clk: sunxi-ng: h6: fix bus clocks' divider position * clk-mvebu-dup: clk: mvebu: ap806: Remove superfluous of_clk_add_provider * clk-davinci: clk: davinci: kill davinci_clk_reset_assert/deassert()

clk: mvebu: ap806: Remove superfluous of_clk_add_provider

2018-10-01T22:13:42+00:00

While applying the commit a8309cedcdce ("clk: apn806: Add eMMC clock to system controller driver"), of_clk_add_provider was added wheres it was already present in the probe function. This extraneous call is harmless but not useful so remove it. Signed-off-by: Gregory CLEMENT Signed-off-by: Stephen Boyd

clk: mvebu: use SPDX-License-Identifier

2018-10-01T22:12:47+00:00

Convert the remaining files to SPDX license description. Signed-off-by: Gregory CLEMENT Signed-off-by: Stephen Boyd

clk: mvebu: ap806: introduce a new binding

2017-06-01T03:03:21+00:00

As for cp110, the initial intent when the binding of the ap806 system controller was to have one flat node. The idea being that what is currently a clock-only driver in drivers would become a MFD driver, exposing the clock, GPIO and pinctrl functionality. However, after taking a step back, this would lead to a messy binding. Indeed, a single node would be a GPIO controller, clock controller, pinmux controller, and more. This patch adopts a more classical solution of a top-level syscon node with sub-nodes for the individual devices. The main benefit will be to have each functional block associated to its own sub-node where we can put its own properties. The introduction of the Armada 7K/8K is still in the early stage so the plan is to remove the old binding. However, we don't want to break the device tree compatibility for the few devices already in the field. For this we still keep the support of the legacy compatible string with a big warning in the kernel about updating the device tree. Acked-by: Rob Herring Signed-off-by: Gregory CLEMENT Signed-off-by: Michael Turquette Link: lkml.kernel.org/r/cc8c8c40fa4c4e71133033358992ec38e5aa2be5.1496239589.git-series.gregory.clement@free-electrons.com