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<title>lwn.git/arch/x86, branch v2.6.31.9</title>
<subtitle>Linux kernel documentation tree maintained by Jonathan Corbet</subtitle>
<id>http://mirrors.hust.edu.cn/git/lwn.git/atom?h=v2.6.31.9</id>
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<updated>2009-12-18T21:44:14+00:00</updated>
<entry>
<title>ACPI: Use the ARB_DISABLE for the CPU which model id is less than 0x0f.</title>
<updated>2009-12-18T21:44:14+00:00</updated>
<author>
<name>Zhao Yakui</name>
<email>yakui.zhao@intel.com</email>
</author>
<published>2009-12-11T07:17:20+00:00</published>
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<id>urn:sha1:7aea74857b397f343696a468e569486cff76ff29</id>
<content type='text'>
commit 03a05ed1152944000151d57b71000de287a1eb02 upstream.

Currently, ARB_DISABLE is a NOP on all of the recent Intel platforms.
For such platforms, reduce contention on c3_lock by skipping the fake
ARB_DISABLE.

The cpu model id on one laptop is 14. If we disable ARB_DISABLE on this box,
the box can't be booted correctly. But if we still enable ARB_DISABLE on this
box, the box can be booted correctly.

So we still use the ARB_DISABLE for the cpu which mode id is less than 0x0f.

http://bugzilla.kernel.org/show_bug.cgi?id=14700

Signed-off-by: Zhao Yakui &lt;yakui.zhao@intel.com&gt;
Acked-by: Venkatesh Pallipadi &lt;venkatesh.pallipadi@intel.com&gt;
Signed-off-by: Len Brown &lt;len.brown@intel.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@suse.de&gt;

</content>
</entry>
<entry>
<title>x86: Under BIOS control, restore AP's APIC_LVTTHMR to the BSP value</title>
<updated>2009-12-18T21:44:12+00:00</updated>
<author>
<name>Yong Wang</name>
<email>yong.y.wang@linux.intel.com</email>
</author>
<published>2009-12-16T05:25:10+00:00</published>
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<id>urn:sha1:a845dbd1d7be1e7cc7bfa2fbaa3fc73933411700</id>
<content type='text'>
Upstream commit a2202aa29289db64ca7988b12343158b67b27f10.

On platforms where bios handles the thermal monitor interrupt,
APIC_LVTTHMR on each logical CPU is programmed to generate a SMI and OS
can't touch it.

Unfortunately AP bringup sequence using INIT-SIPI-SIPI clear all
the LVT entries except the mask bit. Essentially this results in
all LVT entries including the thermal monitoring interrupt set to masked
(clearing the bios programmed value for APIC_LVTTHMR).

And this leads to kernel take over the thermal monitoring interrupt
on AP's but not on BSP (leaving the bios programmed value only on BSP).

As a result of this, we have seen system hangs when the thermal
monitoring interrupt is generated.

Fix this by reading the initial value of thermal LVT entry on BSP
and if bios has taken over the control, then program the same value
on all AP's and leave the thermal monitoring interrupt control
on all the logical cpu's to the bios.

Signed-off-by: Yong Wang &lt;yong.y.wang@intel.com&gt;
Reviewed-by: Suresh Siddha &lt;suresh.b.siddha@intel.com&gt;
Cc: Borislav Petkov &lt;borislav.petkov@amd.com&gt;
Cc: Arjan van de Ven &lt;arjan@infradead.org&gt;
LKML-Reference: &lt;20091110013824.GA24940@ywang-moblin2.bj.intel.com&gt;
Signed-off-by: Ingo Molnar &lt;mingo@elte.hu&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@suse.de&gt;

</content>
</entry>
<entry>
<title>x86/mce: Set up timer unconditionally</title>
<updated>2009-12-18T21:44:10+00:00</updated>
<author>
<name>Jan Beulich</name>
<email>jbeulich@novell.com</email>
</author>
<published>2009-12-08T02:21:37+00:00</published>
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<id>urn:sha1:013fecfdb1d018458327634840f905249dc9b51d</id>
<content type='text'>
commit bc09effabf0c5c6c7021e5ef9af15a23579b32a8 upstream.

mce_timer must be passed to setup_timer() in all cases, no
matter whether it is going to be actually used. Otherwise, when
the CPU gets brought down, its call to del_timer_sync() will
never return, as the timer won't have a base associated, and
hence lock_timer_base() will loop infinitely.

Signed-off-by: Jan Beulich &lt;jbeulich@novell.com&gt;
Signed-off-by: Hidetoshi Seto &lt;seto.hidetoshi@jp.fujitsu.com&gt;
LKML-Reference: &lt;4B1DB831.2030801@jp.fujitsu.com&gt;
Signed-off-by: Ingo Molnar &lt;mingo@elte.hu&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@suse.de&gt;

</content>
</entry>
<entry>
<title>x86: GART: pci-gart_64.c: Use correct length in strncmp</title>
<updated>2009-12-18T21:43:43+00:00</updated>
<author>
<name>Joe Perches</name>
<email>joe@perches.com</email>
</author>
<published>2009-11-10T01:58:50+00:00</published>
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<id>urn:sha1:ca1e562dec3a5a740b775c88eb90c1104545d44b</id>
<content type='text'>
commit 41855b77547fa18d90ed6a5d322983d3fdab1959 upstream.

Signed-off-by: Joe Perches &lt;joe@perches.com&gt;
LKML-Reference: &lt;1257818330.12852.72.camel@Joe-Laptop.home&gt;
Signed-off-by: Ingo Molnar &lt;mingo@elte.hu&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@suse.de&gt;

</content>
</entry>
<entry>
<title>x86: Fix typo in Intel CPU cache size descriptor</title>
<updated>2009-12-18T21:43:43+00:00</updated>
<author>
<name>Dave Jones</name>
<email>davej@redhat.com</email>
</author>
<published>2009-11-10T20:01:20+00:00</published>
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<id>urn:sha1:122bf2b6785292c8ac1bda3dcd438f2a83007ece</id>
<content type='text'>
commit e02e0e1a130b9ca37c5186d38ad4b3aaf58bb149 upstream.

I double-checked the datasheet. One of the existing
descriptors has a typo: it should be 2MB not 2038 KB.

Signed-off-by: Dave Jones &lt;davej@redhat.com&gt;
LKML-Reference: &lt;20091110200120.GA27090@redhat.com&gt;
Signed-off-by: Ingo Molnar &lt;mingo@elte.hu&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@suse.de&gt;

</content>
</entry>
<entry>
<title>x86: Fix iommu=nodac parameter handling</title>
<updated>2009-12-18T21:43:42+00:00</updated>
<author>
<name>Tejun Heo</name>
<email>tj@kernel.org</email>
</author>
<published>2009-10-26T14:41:46+00:00</published>
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<id>urn:sha1:671ca70a2f70399b42e632211f4c9c0c553506e9</id>
<content type='text'>
commit 2ae8bb75db1f3de422eb5898f2a063c46c36dba8 upstream.

iommu=nodac should forbid dac instead of enabling it. Fix it.

Signed-off-by: Tejun Heo &lt;tj@kernel.org&gt;
Acked-by: FUJITA Tomonori &lt;fujita.tomonori@lab.ntt.co.jp&gt;
Cc: Matteo Frigo &lt;athena@fftw.org&gt;
LKML-Reference: &lt;4AE5B52A.4050408@kernel.org&gt;
Signed-off-by: Ingo Molnar &lt;mingo@elte.hu&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@suse.de&gt;

</content>
</entry>
<entry>
<title>x86, Calgary IOMMU quirk: Find nearest matching Calgary while walking up the PCI tree</title>
<updated>2009-12-18T21:43:41+00:00</updated>
<author>
<name>Darrick J. Wong</name>
<email>djwong@us.ibm.com</email>
</author>
<published>2009-12-02T23:05:56+00:00</published>
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<id>urn:sha1:03146ec8b52708f80f1bb5f90d27f090c60541ab</id>
<content type='text'>
commit 4528752f49c1f4025473d12bc5fa9181085c3f22 upstream.

On a multi-node x3950M2 system, there's a slight oddity in the
PCI device tree for all secondary nodes:

 30:1e.0 PCI bridge: Intel Corporation 82801 PCI Bridge (rev e1)
  \-33:00.0 PCI bridge: IBM CalIOC2 PCI-E Root Port (rev 01)
     \-34:00.0 RAID bus controller: LSI Logic / Symbios Logic MegaRAID SAS 1078 (rev 04)

...as compared to the primary node:

 00:1e.0 PCI bridge: Intel Corporation 82801 PCI Bridge (rev e1)
  \-01:00.0 VGA compatible controller: ATI Technologies Inc ES1000 (rev 02)
 03:00.0 PCI bridge: IBM CalIOC2 PCI-E Root Port (rev 01)
  \-04:00.0 RAID bus controller: LSI Logic / Symbios Logic MegaRAID SAS 1078 (rev 04)

In both nodes, the LSI RAID controller hangs off a CalIOC2
device, but on the secondary nodes, the BIOS hides the VGA
device and substitutes the device tree ending with the disk
controller.

It would seem that Calgary devices don't necessarily appear at
the top of the PCI tree, which means that the current code to
find the Calgary IOMMU that goes with a particular device is
buggy.

Rather than walk all the way to the top of the PCI
device tree and try to match bus number with Calgary descriptor,
the code needs to examine each parent of the particular device;
if it encounters a Calgary with a matching bus number, simply
use that.

Otherwise, we BUG() when the bus number of the Calgary doesn't
match the bus number of whatever's at the top of the device tree.

Extra note: This patch appears to work correctly for the x3950
that came before the x3950 M2.

Signed-off-by: Darrick J. Wong &lt;djwong@us.ibm.com&gt;
Acked-by: Muli Ben-Yehuda &lt;muli@il.ibm.com&gt;
Cc: FUJITA Tomonori &lt;fujita.tomonori@lab.ntt.co.jp&gt;
Cc: Joerg Roedel &lt;joerg.roedel@amd.com&gt;
Cc: Yinghai Lu &lt;yhlu.kernel@gmail.com&gt;
Cc: Jon D. Mason &lt;jdmason@kudzu.us&gt;
Cc: Corinna Schultz &lt;coschult@us.ibm.com&gt;
LKML-Reference: &lt;20091202230556.GG10295@tux1.beaverton.ibm.com&gt;
Signed-off-by: Ingo Molnar &lt;mingo@elte.hu&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@suse.de&gt;

</content>
</entry>
<entry>
<title>x86: ASUS P4S800 reboot=bios quirk</title>
<updated>2009-12-18T21:43:40+00:00</updated>
<author>
<name>Leann Ogasawara</name>
<email>leann.ogasawara@canonical.com</email>
</author>
<published>2009-12-04T23:42:22+00:00</published>
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<id>urn:sha1:066658b78bf5c50a6272603824851b327da5646f</id>
<content type='text'>
commit 4832ddda2ec4df96ea1eed334ae2dbd65fc1f541 upstream.

Bug reporter noted their system with an ASUS P4S800 motherboard would
hang when rebooting unless reboot=b was specified.  Their dmidecode
didn't contain descriptive System Information for Manufacturer or
Product Name, so I used their Base Board Information to create a
reboot quirk patch.  The bug reporter confirmed this patch resolves
the reboot hang.

Handle 0x0001, DMI type 1, 25 bytes
System Information
       Manufacturer: System Manufacturer
       Product Name: System Name
       Version: System Version
       Serial Number: SYS-1234567890
       UUID: E0BFCD8B-7948-D911-A953-E486B4EEB67F
       Wake-up Type: Power Switch

Handle 0x0002, DMI type 2, 8 bytes
Base Board Information
     Manufacturer: ASUSTeK Computer INC.
     Product Name: P4S800
     Version: REV 1.xx
     Serial Number: xxxxxxxxxxx

BugLink: http://bugs.launchpad.net/bugs/366682

ASUS P4S800 will hang when rebooting unless reboot=b is specified.
Add a quirk to reboot through the bios.

Signed-off-by: Leann Ogasawara &lt;leann.ogasawara@canonical.com&gt;
LKML-Reference: &lt;1259972107.4629.275.camel@emiko&gt;
Signed-off-by: H. Peter Anvin &lt;hpa@zytor.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@suse.de&gt;

</content>
</entry>
<entry>
<title>x86, apic: Enable lapic nmi watchdog on AMD Family 11h</title>
<updated>2009-12-18T21:43:39+00:00</updated>
<author>
<name>Mikael Pettersson</name>
<email>mikpe@it.uu.se</email>
</author>
<published>2009-12-03T14:52:44+00:00</published>
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<id>urn:sha1:8a44f81934aa1d687551dc20077dcb82af02b8a4</id>
<content type='text'>
commit 7d1849aff6687a135a8da3a75e32a00e3137a5e2 upstream.

The x86 lapic nmi watchdog does not recognize AMD Family 11h,
resulting in:

  NMI watchdog: CPU not supported

As far as I can see from available documentation (the BKDM),
family 11h looks identical to family 10h as far as the PMU
is concerned.

Extending the check to accept family 11h results in:

  Testing NMI watchdog ... OK.

I've been running with this change on a Turion X2 Ultra ZM-82
laptop for a couple of weeks now without problems.

Signed-off-by: Mikael Pettersson &lt;mikpe@it.uu.se&gt;
Cc: Andreas Herrmann &lt;andreas.herrmann3@amd.com&gt;
Cc: Joerg Roedel &lt;joerg.roedel@amd.com&gt;
LKML-Reference: &lt;19223.53436.931768.278021@pilspetsen.it.uu.se&gt;
Signed-off-by: Ingo Molnar &lt;mingo@elte.hu&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@suse.de&gt;

</content>
</entry>
<entry>
<title>x86/amd-iommu: un__init iommu_setup_msi</title>
<updated>2009-12-18T21:43:38+00:00</updated>
<author>
<name>Joerg Roedel</name>
<email>joerg.roedel@amd.com</email>
</author>
<published>2009-11-23T11:45:25+00:00</published>
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<id>urn:sha1:c165ffd0ee7e641d104fd419109be30edcf2622c</id>
<content type='text'>
commit 9f800de38b05d84809e89f16671d636a140eede7 upstream.

This function may be called on the resume path and can not
be dropped after booting.

Signed-off-by: Joerg Roedel &lt;joerg.roedel@amd.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@suse.de&gt;

</content>
</entry>
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