<feed xmlns='http://www.w3.org/2005/Atom'>
<title>lwn.git/arch/x86/kernel/apic/apic.c, branch v6.9</title>
<subtitle>Linux kernel documentation tree maintained by Jonathan Corbet</subtitle>
<id>http://mirrors.hust.edu.cn/git/lwn.git/atom?h=v6.9</id>
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<updated>2024-04-30T05:51:34+00:00</updated>
<entry>
<title>x86/apic: Don't access the APIC when disabling x2APIC</title>
<updated>2024-04-30T05:51:34+00:00</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2024-04-25T22:30:36+00:00</published>
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<id>urn:sha1:720a22fd6c1cdadf691281909950c0cbc5cdf17e</id>
<content type='text'>
With 'iommu=off' on the kernel command line and x2APIC enabled by the BIOS
the code which disables the x2APIC triggers an unchecked MSR access error:

  RDMSR from 0x802 at rIP: 0xffffffff94079992 (native_apic_msr_read+0x12/0x50)

This is happens because default_acpi_madt_oem_check() selects an x2APIC
driver before the x2APIC is disabled.

When the x2APIC is disabled because interrupt remapping cannot be enabled
due to 'iommu=off' on the command line, x2apic_disable() invokes
apic_set_fixmap() which in turn tries to read the APIC ID. This triggers
the MSR warning because x2APIC is disabled, but the APIC driver is still
x2APIC based.

Prevent that by adding an argument to apic_set_fixmap() which makes the
APIC ID read out conditional and set it to false from the x2APIC disable
path. That's correct as the APIC ID has already been read out during early
discovery.

Fixes: d10a904435fa ("x86/apic: Consolidate boot_cpu_physical_apicid initialization sites")
Reported-by: Adrian Huang &lt;ahuang12@lenovo.com&gt;
Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Signed-off-by: Borislav Petkov (AMD) &lt;bp@alien8.de&gt;
Signed-off-by: Ingo Molnar &lt;mingo@kernel.org&gt;
Tested-by: Adrian Huang &lt;ahuang12@lenovo.com&gt;
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/875xw5t6r7.ffs@tglx
</content>
</entry>
<entry>
<title>x86/bugs: Rename various 'ia32_cap' variables to 'x86_arch_cap_msr'</title>
<updated>2024-04-11T08:30:33+00:00</updated>
<author>
<name>Ingo Molnar</name>
<email>mingo@kernel.org</email>
</author>
<published>2024-04-11T07:25:36+00:00</published>
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<id>urn:sha1:d0485730d2189ffe5d986d4e9e191f1e4d5ffd24</id>
<content type='text'>
So we are using the 'ia32_cap' value in a number of places,
which got its name from MSR_IA32_ARCH_CAPABILITIES MSR register.

But there's very little 'IA32' about it - this isn't 32-bit only
code, nor does it originate from there, it's just a historic
quirk that many Intel MSR names are prefixed with IA32_.

This is already clear from the helper method around the MSR:
x86_read_arch_cap_msr(), which doesn't have the IA32 prefix.

So rename 'ia32_cap' to 'x86_arch_cap_msr' to be consistent with
its role and with the naming of the helper function.

Signed-off-by: Ingo Molnar &lt;mingo@kernel.org&gt;
Cc: Josh Poimboeuf &lt;jpoimboe@redhat.com&gt;
Cc: Nikolay Borisov &lt;nik.borisov@suse.com&gt;
Cc: Linus Torvalds &lt;torvalds@linux-foundation.org&gt;
Cc: Sean Christopherson &lt;seanjc@google.com&gt;
Link: https://lore.kernel.org/r/9592a18a814368e75f8f4b9d74d3883aa4fd1eaf.1712813475.git.jpoimboe@kernel.org
</content>
</entry>
<entry>
<title>x86/cpu/topology: Confine topology information</title>
<updated>2024-02-15T21:07:42+00:00</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2024-02-13T21:05:46+00:00</published>
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<id>urn:sha1:58aa34abe9954cd5dfbf322fc612146c5f45e52b</id>
<content type='text'>
Now that all external fiddling with num_processors and disabled_cpus is
gone, move the last user prefill_possible_map() into the topology code too
and remove the global visibility of these variables.

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Tested-by: Michael Kelley &lt;mhklinux@outlook.com&gt;
Tested-by: Sohil Mehta &lt;sohil.mehta@intel.com&gt;
Link: https://lore.kernel.org/r/20240213210251.994756960@linutronix.de



</content>
</entry>
<entry>
<title>x86/cpu/topology: Move registration out of APIC code</title>
<updated>2024-02-15T21:07:41+00:00</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2024-02-13T21:05:35+00:00</published>
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<id>urn:sha1:c0a66c2847908e41c771ca2355fba935a82a9f62</id>
<content type='text'>
The APIC/CPU registration sits in the middle of the APIC code. In fact this
is a topology evaluation function and has nothing to do with the inner
workings of the local APIC.

Move it out into a file which reflects what this is about.

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Tested-by: Michael Kelley &lt;mhklinux@outlook.com&gt;
Tested-by: Sohil Mehta &lt;sohil.mehta@intel.com&gt;
Link: https://lore.kernel.org/r/20240213210251.543948812@linutronix.de



</content>
</entry>
<entry>
<title>x86/apic: Use a proper define for invalid ACPI CPU ID</title>
<updated>2024-02-15T21:07:41+00:00</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2024-02-13T21:05:21+00:00</published>
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<id>urn:sha1:1a5d0f62d10d5da44c2b6a97b6600dea8a7519fb</id>
<content type='text'>
The ACPI ID for CPUs is preset with U32_MAX which is completely non
obvious. Use a proper define for it.

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Tested-by: Michael Kelley &lt;mhklinux@outlook.com&gt;
Tested-by: Sohil Mehta &lt;sohil.mehta@intel.com&gt;
Link: https://lore.kernel.org/r/20240212154640.177504138@linutronix.de



</content>
</entry>
<entry>
<title>x86/apic: Remove yet another dubious callback</title>
<updated>2024-02-15T21:07:41+00:00</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2024-02-13T21:05:20+00:00</published>
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<id>urn:sha1:4a5f72a4a39f5d5dcf9b9dc1acc57ecbbb8d4caa</id>
<content type='text'>
Paranoia is not wrong, but having an APIC callback which is in most
implementations a complete NOOP and in one actually looking whether the
APICID of an upcoming CPU has been registered. The same APICID which was
used to bring the CPU out of wait for startup.

That's paranoia for the paranoia sake. Remove the voodoo.

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Tested-by: Michael Kelley &lt;mhklinux@outlook.com&gt;
Tested-by: Sohil Mehta &lt;sohil.mehta@intel.com&gt;
Link: https://lore.kernel.org/r/20240212154640.116510935@linutronix.de



</content>
</entry>
<entry>
<title>x86/apic: Remove the pointless writeback of boot_cpu_physical_apicid</title>
<updated>2024-02-15T21:07:41+00:00</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2024-02-13T21:05:19+00:00</published>
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<id>urn:sha1:58d16928358f91d48421838a7484321b3149130d</id>
<content type='text'>
There is absolutely no point to write the APIC ID which was read from the
local APIC earlier, back into the local APIC for the 64-bit UP case.

Remove that along with the apic callback which is solely there for this
pointless exercise.

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Tested-by: Michael Kelley &lt;mhklinux@outlook.com&gt;
Tested-by: Sohil Mehta &lt;sohil.mehta@intel.com&gt;
Link: https://lore.kernel.org/r/20240212154640.055288922@linutronix.de



</content>
</entry>
<entry>
<title>x86/mpparse: Remove the physid_t bitmap wrapper</title>
<updated>2024-02-15T21:07:41+00:00</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2024-02-13T21:05:17+00:00</published>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/commit/?id=350b5e2730d1e15337a10bd913694ee4527c02f0'/>
<id>urn:sha1:350b5e2730d1e15337a10bd913694ee4527c02f0</id>
<content type='text'>
physid_t is a wrapper around bitmap. Just remove the onion layer and use
bitmap functionality directly.

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Tested-by: Michael Kelley &lt;mhklinux@outlook.com&gt;
Tested-by: Sohil Mehta &lt;sohil.mehta@intel.com&gt;
Link: https://lore.kernel.org/r/20240212154639.994904510@linutronix.de



</content>
</entry>
<entry>
<title>x86/apic: Get rid of get_physical_broadcast()</title>
<updated>2024-02-15T21:07:39+00:00</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2024-02-13T21:04:56+00:00</published>
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<id>urn:sha1:517234446c1ad1d6bb0d9f5b94a71b24f80edaae</id>
<content type='text'>
There is no point for this function. The only case where this is used is
when there is no XAPIC available, which means the broadcast address is 0xF.

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Tested-by: Michael Kelley &lt;mhklinux@outlook.com&gt;
Tested-by: Sohil Mehta &lt;sohil.mehta@intel.com&gt;
Link: https://lore.kernel.org/r/20240212154639.057209154@linutronix.de

</content>
</entry>
<entry>
<title>arch/x86: Fix typos</title>
<updated>2024-01-03T10:46:22+00:00</updated>
<author>
<name>Bjorn Helgaas</name>
<email>bhelgaas@google.com</email>
</author>
<published>2024-01-03T00:40:11+00:00</published>
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<id>urn:sha1:54aa699e8094efb7d7675fefbc03dfce24f98456</id>
<content type='text'>
Fix typos, most reported by "codespell arch/x86".  Only touches comments,
no code changes.

Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Signed-off-by: Ingo Molnar &lt;mingo@kernel.org&gt;
Reviewed-by: Randy Dunlap &lt;rdunlap@infradead.org&gt;
Link: https://lore.kernel.org/r/20240103004011.1758650-1-helgaas@kernel.org
</content>
</entry>
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