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<title>lwn.git/arch/tile/kernel/pci.c, branch docs-next</title>
<subtitle>Linux kernel documentation tree maintained by Jonathan Corbet</subtitle>
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<updated>2018-03-16T09:56:03+00:00</updated>
<entry>
<title>arch: remove tile port</title>
<updated>2018-03-16T09:56:03+00:00</updated>
<author>
<name>Arnd Bergmann</name>
<email>arnd@arndb.de</email>
</author>
<published>2018-03-09T13:13:42+00:00</published>
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<id>urn:sha1:bb9d812643d8a121df7d614a2b9c60193a92deb0</id>
<content type='text'>
The Tile architecture port was added by Chris Metcalf in 2010, and
maintained until early 2018 when he orphaned it due to his departure
from Mellanox, and nobody else stepped up to maintain it. The product
line is still around in the form of the BlueField SoC, but no longer
uses the Tile architecture.

There are also still products for sale with Tile-GX SoCs, notably the
Mikrotik CCR router family. The products all use old (linux-3.3) kernels
with lots of patches and won't be upgraded by their manufacturers. There
have been efforts to port both OpenWRT and Debian to these, but both
projects have stalled and are very unlikely to be continued in the future.

Given that we are reasonably sure that nobody is still using the port
with an upstream kernel any more, it seems better to remove it now while
the port is in a good shape than to let it bitrot for a few years first.

Cc: Chris Metcalf &lt;chris.d.metcalf@gmail.com&gt;
Cc: John Paul Adrian Glaubitz &lt;glaubitz@physik.fu-berlin.de&gt;
Link: http://www.mellanox.com/page/npu_multicore_overview
Link: https://jenkins.debian.net/view/rebootstrap/job/rebootstrap_tilegx_gcc7/
Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</content>
</entry>
<entry>
<title>Merge branch 'pci/resource' into next</title>
<updated>2017-09-07T18:24:19+00:00</updated>
<author>
<name>Bjorn Helgaas</name>
<email>bhelgaas@google.com</email>
</author>
<published>2017-09-07T18:24:19+00:00</published>
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<id>urn:sha1:9198407e23ec89f0e1562f439771aeea83345d0d</id>
<content type='text'>
* pci/resource:
  microblaze/PCI: Remove pcibios_setup_bus_{self/devices} dead code
  ARC: Remove empty kernel/pcibios.c
  PCI: Add a generic weak pcibios_align_resource()
  PCI: Add a generic weak pcibios_fixup_bus()
</content>
</entry>
<entry>
<title>tile/PCI: Replace pci_fixup_irqs() call with host bridge IRQ mapping hooks</title>
<updated>2017-08-03T21:28:56+00:00</updated>
<author>
<name>Lorenzo Pieralisi</name>
<email>lorenzo.pieralisi@arm.com</email>
</author>
<published>2017-07-31T16:37:54+00:00</published>
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<id>urn:sha1:98611dd735b472c23cc1e8cca90a997393a3a955</id>
<content type='text'>
The pci_fixup_irqs() function allocates IRQs for all PCI devices present in
a system; those PCI devices possibly belong to different PCI bus trees (and
possibly rooted at different host bridges) and may well be enabled (ie
probed and bound to a driver) by the time pci_fixup_irqs() is called when
probing a given host bridge driver.

Furthermore, current kernel code relying on pci_fixup_irqs() to assign
legacy PCI IRQs to devices does not work at all for hotplugged devices in
that the code carrying out the IRQ fixup is called at host bridge driver
probe time, which just cannot take into account devices hotplugged after
the system has booted.

The introduction of map/swizzle function hooks in struct pci_host_bridge
allows us to define per-bridge map/swizzle functions that can be used at
device probe time in PCI core code to allocate IRQs for a given device
(through pci_assign_irq()).

Convert PCI host bridge initialization code to the
pci_scan_root_bus_bridge() API (that allows to pass a struct
pci_host_bridge with initializedmap/swizzle pointers) and remove the
pci_fixup_irqs() call from arch code.

Signed-off-by: Lorenzo Pieralisi &lt;lorenzo.pieralisi@arm.com&gt;
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Cc: Chris Metcalf &lt;cmetcalf@mellanox.com&gt;</content>
</entry>
<entry>
<title>PCI: Add a generic weak pcibios_align_resource()</title>
<updated>2017-08-02T19:53:16+00:00</updated>
<author>
<name>Palmer Dabbelt</name>
<email>palmer@dabbelt.com</email>
</author>
<published>2017-08-02T19:44:50+00:00</published>
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<id>urn:sha1:ecf677c8dcaa7bf13eee31b4d9e4639d559984ad</id>
<content type='text'>
Multiple architectures define this as a trivial function, and I'm adding
another one as part of the RISC-V port.  Add a __weak version of
pcibios_align_resource() and delete the now-obselete ones in a handful of
ports.

The only functional change should be that a handful of ports used to export
pcibios_fixup_bus().  Only some architectures export this, so I just
dropped it.

Signed-off-by: Palmer Dabbelt &lt;palmer@dabbelt.com&gt;
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;</content>
</entry>
<entry>
<title>PCI: Add a generic weak pcibios_fixup_bus()</title>
<updated>2017-08-02T19:43:38+00:00</updated>
<author>
<name>Palmer Dabbelt</name>
<email>palmer@dabbelt.com</email>
</author>
<published>2017-06-24T01:50:42+00:00</published>
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<id>urn:sha1:bccf90d6e063d278b9ddc78dd266d0adef29886c</id>
<content type='text'>
Multiple architectures define this as an empty function, and I'm adding
another one as part of the RISC-V port.  Add a __weak version of
pcibios_fixup_bus() and delete the now-obselete ones in a handful of
ports.

The only functional change should be that microblaze used to export
pcibios_fixup_bus().  None of the other architectures exports this, so I
just dropped it.

Signed-off-by: Palmer Dabbelt &lt;palmer@dabbelt.com&gt;
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;</content>
</entry>
<entry>
<title>tile: use __ro_after_init instead of tile-specific __write_once</title>
<updated>2016-12-16T20:32:29+00:00</updated>
<author>
<name>Chris Metcalf</name>
<email>cmetcalf@mellanox.com</email>
</author>
<published>2016-11-07T19:19:10+00:00</published>
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<id>urn:sha1:14e73e78ee982710292248536aa84cba41e974f4</id>
<content type='text'>
The semantics of the old tile __write_once are the same as the
newer generic __ro_after_init, so rename them all and get rid
of the tile-specific version.

This does not enable actual support for __ro_after_init,
which had been dropped from the tile architecture before the
initial upstreaming was done, since we had at that time switched
to using 16MB huge pages to map the kernel.

Signed-off-by: Chris Metcalf &lt;cmetcalf@mellanox.com&gt;
</content>
</entry>
<entry>
<title>PCI: Assign resources before drivers claim devices (pci_scan_root_bus())</title>
<updated>2015-03-19T15:17:13+00:00</updated>
<author>
<name>Yijing Wang</name>
<email>wangyijing@huawei.com</email>
</author>
<published>2015-03-16T03:18:56+00:00</published>
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<id>urn:sha1:b97ea289cf6aff8d4cbcefe2b707bb9b00a73c73</id>
<content type='text'>
Previously, pci_scan_root_bus() created a root PCI bus, enumerated the
devices on it, and called pci_bus_add_devices(), which made the devices
available for drivers to claim them.

Most callers assigned resources to devices after pci_scan_root_bus()
returns, which may be after drivers have claimed the devices.  This is
incorrect; the PCI core should not change device resources while a driver
is managing the device.

Remove pci_bus_add_devices() from pci_scan_root_bus() and do it after any
resource assignment in the callers.

Note that ARM's pci_common_init_dev() already called pci_bus_add_devices()
after pci_scan_root_bus(), so we only need to remove the first call:

  pci_common_init_dev
    pcibios_init_hw
      pci_scan_root_bus
        pci_bus_add_devices        # first call
    pci_bus_assign_resources
    pci_bus_add_devices            # second call

[bhelgaas: changelog, drop "root_bus" var in alpha common_init_pci(),
return failure earlier in mn10300, add "return" in x86 pcibios_scan_root(),
return early if xtensa platform_pcibios_fixup() fails]
Signed-off-by: Yijing Wang &lt;wangyijing@huawei.com&gt;
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
CC: Richard Henderson &lt;rth@twiddle.net&gt;
CC: Ivan Kokshaysky &lt;ink@jurassic.park.msu.ru&gt;
CC: Matt Turner &lt;mattst88@gmail.com&gt;
CC: David Howells &lt;dhowells@redhat.com&gt;
CC: Tony Luck &lt;tony.luck@intel.com&gt;
CC: Michal Simek &lt;monstr@monstr.eu&gt;
CC: Ralf Baechle &lt;ralf@linux-mips.org&gt;
CC: Koichi Yasutake &lt;yasutake.koichi@jp.panasonic.com&gt;
CC: Sebastian Ott &lt;sebott@linux.vnet.ibm.com&gt;
CC: "David S. Miller" &lt;davem@davemloft.net&gt;
CC: Chris Metcalf &lt;cmetcalf@ezchip.com&gt;
CC: Chris Zankel &lt;chris@zankel.net&gt;
CC: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
CC: Thomas Gleixner &lt;tglx@linutronix.de&gt;
</content>
</entry>
<entry>
<title>tile: use PCI define for Max_Read_Request_Size</title>
<updated>2015-01-27T14:14:26+00:00</updated>
<author>
<name>Rafał Miłecki</name>
<email>zajec5@gmail.com</email>
</author>
<published>2015-01-26T17:06:12+00:00</published>
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<id>urn:sha1:ff59887f2de1692e7691004858adba3febcade20</id>
<content type='text'>
Replace a magic number with a PCI #define symbol.

Signed-off-by: Rafał Miłecki &lt;zajec5@gmail.com&gt;
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Acked-by: Chris Metcalf &lt;cmetcalf@ezchip.com&gt;</content>
</entry>
<entry>
<title>tile: Use the more common pr_warn instead of pr_warning</title>
<updated>2014-11-11T20:51:42+00:00</updated>
<author>
<name>Joe Perches</name>
<email>joe@perches.com</email>
</author>
<published>2014-10-31T17:50:46+00:00</published>
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<id>urn:sha1:f47436734dc89ece62654d4db8d08163a89dd7ca</id>
<content type='text'>
And other message logging neatening.

Other miscellanea:

o coalesce formats
o realign arguments
o standardize a couple of macros
o use __func__ instead of embedding the function name

Signed-off-by: Joe Perches &lt;joe@perches.com&gt;
Signed-off-by: Chris Metcalf &lt;cmetcalf@tilera.com&gt;
</content>
</entry>
<entry>
<title>arch/tile: remove unused variable 'devcap'</title>
<updated>2014-04-04T17:11:40+00:00</updated>
<author>
<name>Chris Metcalf</name>
<email>cmetcalf@tilera.com</email>
</author>
<published>2014-04-04T17:11:40+00:00</published>
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<id>urn:sha1:5eb0bdf84433eb7b7ad4ba92a80aac57ad4b46ea</id>
<content type='text'>
Commit 503275bf37 removed the use of the variable but not
the variable itself.

Signed-off-by: Chris Metcalf &lt;cmetcalf@tilera.com&gt;
</content>
</entry>
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