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<title>lwn.git/arch/sparc64/kernel/traps.c, branch docs-5.10-3</title>
<subtitle>Linux kernel documentation tree maintained by Jonathan Corbet</subtitle>
<id>http://mirrors.hust.edu.cn/git/lwn.git/atom?h=docs-5.10-3</id>
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<updated>2008-12-04T17:17:21+00:00</updated>
<entry>
<title>sparc,sparc64: unify kernel/</title>
<updated>2008-12-04T17:17:21+00:00</updated>
<author>
<name>Sam Ravnborg</name>
<email>sam@ravnborg.org</email>
</author>
<published>2008-12-03T11:11:52+00:00</published>
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<id>urn:sha1:a88b5ba8bd8ac18aad65ee6c6a254e2e74876db3</id>
<content type='text'>
o Move all files from sparc64/kernel/ to sparc/kernel
  - rename as appropriate
o Update sparc/Makefile to the changes
o Update sparc/kernel/Makefile to include the sparc64 files

NOTE: This commit changes link order on sparc64!

Link order had to change for either of sparc32 and sparc64.
And assuming sparc64 see more testing than sparc32 change link
order on sparc64 where issues will be caught faster.

Signed-off-by: Sam Ravnborg &lt;sam@ravnborg.org&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>sparc64: Make %pil level 15 a pseudo-NMI.</title>
<updated>2008-12-04T17:17:02+00:00</updated>
<author>
<name>David S. Miller</name>
<email>davem@davemloft.net</email>
</author>
<published>2008-11-24T05:55:29+00:00</published>
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<id>urn:sha1:b4f4372f96e0573d752d9e45beda02fabf716cc8</id>
<content type='text'>
So that we can profile code even in a local_irq_disable() section,
only write 14 (instead of 15) into the %pil register to disable IRQs.

This allows PIL level 15 to serve as a pseudo NMI.

Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>sparc64: Stop using memory barriers for atomics and locks.</title>
<updated>2008-12-04T17:16:47+00:00</updated>
<author>
<name>David S. Miller</name>
<email>davem@davemloft.net</email>
</author>
<published>2008-11-15T21:33:25+00:00</published>
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<id>urn:sha1:293666b7a17cb7a389fc274980439212386a19c4</id>
<content type='text'>
The kernel always executes in the TSO memory model now,
so none of this stuff is necessary any more.

With helpful feedback from Nick Piggin.

Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/torvalds/linux-2.6</title>
<updated>2008-10-11T19:39:35+00:00</updated>
<author>
<name>David S. Miller</name>
<email>davem@davemloft.net</email>
</author>
<published>2008-10-11T19:39:35+00:00</published>
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<id>urn:sha1:56c5d900dbb8e042bfad035d18433476931d8f93</id>
<content type='text'>
Conflicts:

	sound/core/memalloc.c
</content>
</entry>
<entry>
<title>sparc64: Fix SMP bootup with CONFIG_STACK_DEBUG or ftrace.</title>
<updated>2008-09-16T18:44:00+00:00</updated>
<author>
<name>David S. Miller</name>
<email>davem@davemloft.net</email>
</author>
<published>2008-09-16T18:44:00+00:00</published>
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<id>urn:sha1:9843099ff46467461d6476a827f6f9701682dbac</id>
<content type='text'>
Based upon a report by Meelis Roos.

Any function call can try to access the current
thread register via the _mcount hooks when the kernel
is built with -pg (via ftrace or STACK_DEBUG).

That can't be setup properly very early on during
the bootup of other cpus for sun4u and some early
sun4v systems.

So add notrace markers to these specific functions, so
that _mcount doesn't get invoked too early.

Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>sparc64: Fix sparse warnings in pci.c</title>
<updated>2008-09-12T06:57:40+00:00</updated>
<author>
<name>David S. Miller</name>
<email>davem@davemloft.net</email>
</author>
<published>2008-09-12T06:57:40+00:00</published>
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<id>urn:sha1:77d10d0e63dcc4f961cb416447d64281300e5a01</id>
<content type='text'>
1) Declare pci_poke_* in pci_impl.h
2) of_create_pci_dev() should be static
3) -&gt;setup_msi_irq() wants an unsigned int pointer not a plain
   int one
4) void value expression return in arch_teardown_msi_irq()

Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>sparc64: Fix sparse warnings in visemul.c</title>
<updated>2008-09-12T06:46:40+00:00</updated>
<author>
<name>David S. Miller</name>
<email>davem@davemloft.net</email>
</author>
<published>2008-09-12T06:46:40+00:00</published>
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<id>urn:sha1:7e0b1e6186c755becf8b19c844c63db1a551898b</id>
<content type='text'>
1) edge8 tables should be static
2) add vis_emul() extern decl. to asm/visasm.h

Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>sparc64: Allow chmc to be built as a module.</title>
<updated>2008-08-25T05:17:29+00:00</updated>
<author>
<name>David S. Miller</name>
<email>davem@davemloft.net</email>
</author>
<published>2008-08-25T05:17:29+00:00</published>
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<id>urn:sha1:41660e9ac639c97840258d3c5294f618ca8cc46f</id>
<content type='text'>
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>sparc64: Add generic interface for registering a dimm printing handler.</title>
<updated>2008-08-25T05:08:34+00:00</updated>
<author>
<name>David S. Miller</name>
<email>davem@davemloft.net</email>
</author>
<published>2008-08-25T05:08:34+00:00</published>
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<id>urn:sha1:881d021ab0d675f519b68df916fde969940ef988</id>
<content type='text'>
The way to do this varies by platform type and the exact memory
controller the cpu uses.

For Spitfire cpus we currently just use prom_getunumber() and hope
that works.

For Cheetah cpus we have a memory controller driver that can
compute this information.

Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>sparc64: Implement IRQ stacks.</title>
<updated>2008-08-13T01:33:56+00:00</updated>
<author>
<name>David S. Miller</name>
<email>davem@davemloft.net</email>
</author>
<published>2008-08-13T01:33:56+00:00</published>
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<id>urn:sha1:4f70f7a91bffdcc39f088748dc678953eb9a3fbd</id>
<content type='text'>
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
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