lwn.git/arch/sparc64/kernel/sun4v_ivec.S, branch v3.4.17

sparc,sparc64: unify kernel/

2008-12-04T17:17:21+00:00

o Move all files from sparc64/kernel/ to sparc/kernel - rename as appropriate o Update sparc/Makefile to the changes o Update sparc/kernel/Makefile to include the sparc64 files NOTE: This commit changes link order on sparc64! Link order had to change for either of sparc32 and sparc64. And assuming sparc64 see more testing than sparc32 change link order on sparc64 where issues will be caught faster. Signed-off-by: Sam Ravnborg Signed-off-by: David S. Miller

sparc64: Make %pil level 15 a pseudo-NMI.

2008-12-04T17:17:02+00:00

So that we can profile code even in a local_irq_disable() section, only write 14 (instead of 15) into the %pil register to disable IRQs. This allows PIL level 15 to serve as a pseudo NMI. Signed-off-by: David S. Miller

[SPARC64]: Use sun4v VIRQ interfaces as intended.

2007-10-14T04:53:16+00:00

We were simply concatenating the devhandle and devino and using that as the cookie, which defeats the entire purpose of the VIRQ hypervisor interfaces. Now that we use physical addresses for the INO buckets, we can allocate them dynamically for VIRQs and encode the cookies as ~__pa(bucket). This allows us to test for and decode the cookie with a simple: brlz $reg1, 1f xnor $reg1, %g0, $reg2 sequence. This works because bit 64 is never set in traditional INO vectors, and it is also never set in a physical address. So xnor'ing the physical address of the bucket always gives us a negative number, and thus a unique condition we can test cheaply. Inspired by ideas from Greg Onufer. Signed-off-by: David S. Miller

[SPARC64]: Access ivector_table[] using physical addresses.

2007-10-14T04:53:15+00:00

Signed-off-by: David S. Miller

[SPARC64]: Make IVEC pointers 64-bit.

2007-10-14T04:53:15+00:00

Currently we chain IVEC entries using 32-bit "pointers" because we know that the ivector_table is in the main kernel image, thus below 4GB. This uses proper 64-bit pointers instead. Whilst this bloats up the kernel image size, this sets the infrastructure necessary to significantly shrink the kernel size by using physical addresses and dynamically allocating the ivector table. Signed-off-by: David S. Miller

[SPARC64]: Use machine description and OBP properly for cpu probing.

2007-05-29T09:49:41+00:00

Signed-off-by: David S. Miller

[SPARC64]: Add irqtrace/stacktrace/lockdep support.

2006-12-10T10:39:09+00:00

Signed-off-by: David S. Miller

[SPARC64]: Move over to GENERIC_HARDIRQS.

2006-06-20T08:23:32+00:00

This is the long overdue conversion of sparc64 over to the generic IRQ layer. The kernel image is slightly larger, but the BSS is ~60K smaller due to the reduced size of struct ino_bucket. A lot of IRQ implementation details, including ino_bucket, were moved out of asm-sparc64/irq.h and are now private to arch/sparc64/kernel/irq.c, and most of the code in irq.c totally disappeared. One thing that's different at the moment is IRQ distribution, we do it at enable_irq() time. If the cpu mask is ALL then we round-robin using a global rotating cpu counter, else we pick the first cpu in the mask to support single cpu targetting. This is similar to what powerpc's XICS IRQ support code does. This works fine on my UP SB1000, and the SMP build goes fine and runs on that machine, but lots of testing on different setups is needed. Signed-off-by: David S. Miller

[SPARC64]: Send all device interrupts via one PIL.

2006-06-20T08:20:00+00:00

This is the first in a series of cleanups that will hopefully allow a seamless attempt at using the generic IRQ handling infrastructure in the Linux kernel. Define PIL_DEVICE_IRQ and vector all device interrupts through there. Get rid of the ugly pil0_dummy_{bucket,desc}, instead vector the timer interrupt directly to a specific handler since the timer interrupt is the only event that will be signaled on PIL 14. The irq_worklist is now in the per-cpu trap_block[]. Signed-off-by: David S. Miller

[SPARC64]: Use TRAP_LOAD_IRQ_WORK() in sun4v device mondo handler.

2006-03-20T09:12:49+00:00

Signed-off-by: David S. Miller