lwn.git/arch/loongarch/include/asm/kvm_pch_pic.h, branch masterLinux kernel documentation tree maintained by Jonathan Corbethttp://mirrors.hust.edu.cn/git/lwn.git/atom?h=master2026-04-09T10:56:37+00:00LoongArch: KVM: Add DMSINTC inject msi to vCPU2026-04-09T10:56:37+00:00Song Gaogaosong@loongson.cn2026-04-09T10:56:37+00:00urn:sha1:03de5eecb0f0f68f29086bc0075c7fd597bf4e4a
Implement irqfd that deliver msi to vCPU and vCPU dmsintc irq injection.
Add pch_msi_set_irq() choice dmsintc to set msi irq by the msg_addr and
implement dmsintc set msi irq.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
LoongArch: KVM: Set version information at initial stage2025-09-23T15:37:09+00:00Bibo Maomaobibo@loongson.cn2025-09-23T15:37:09+00:00urn:sha1:2f412eb7650c369744420cc2d06404fe3f1fb79f
Register PCH_PIC_INT_ID constains version and supported irq number
information, and it is a read only register. The detailed value can
be set at initial stage, rather than read callback.
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
LoongArch: KVM: Add PCHPIC read and write functions2024-11-13T08:18:27+00:00Xianglai Lilixianglai@loongson.cn2024-11-13T08:18:27+00:00urn:sha1:f5f31efa3c2d51c03afab5ab6e3f004d2d529013
Add implementation of IPI interrupt controller's address space read and
write function simulation.
Implement interrupt injection interface under loongarch.
Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn>
Signed-off-by: Xianglai Li <lixianglai@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
LoongArch: KVM: Add PCHPIC device support2024-11-13T08:18:27+00:00Xianglai Lilixianglai@loongson.cn2024-11-13T08:18:27+00:00urn:sha1:e785dfacf7e7fe94370fa0e8e3ff1bc8fe179831
Add device model for PCHPIC interrupt controller, implemente basic
create & destroy interface, and register device model to kvm device
table.
Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn>
Signed-off-by: Xianglai Li <lixianglai@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>