<feed xmlns='http://www.w3.org/2005/Atom'>
<title>lwn.git/arch/arm64/boot/dts/qcom/sm4450.dtsi, branch docs-next</title>
<subtitle>Linux kernel documentation tree maintained by Jonathan Corbet</subtitle>
<id>http://mirrors.hust.edu.cn/git/lwn.git/atom?h=docs-next</id>
<link rel='self' href='http://mirrors.hust.edu.cn/git/lwn.git/atom?h=docs-next'/>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/'/>
<updated>2026-03-26T14:40:59+00:00</updated>
<entry>
<title>arm64: dts: qcom: Drop CPU masks from GICv3 PPI interrupts</title>
<updated>2026-03-26T14:40:59+00:00</updated>
<author>
<name>Geert Uytterhoeven</name>
<email>geert+renesas@glider.be</email>
</author>
<published>2026-03-04T17:11:04+00:00</published>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/commit/?id=ec6944df7b58045ecbdbf6962b89c7f28df9c5b6'/>
<id>urn:sha1:ec6944df7b58045ecbdbf6962b89c7f28df9c5b6</id>
<content type='text'>
Unlike older GIC variants, the GICv3 DT bindings do not support
specifying a CPU mask in PPI interrupt specifiers.  Drop the masks.

Signed-off-by: Geert Uytterhoeven &lt;geert+renesas@glider.be&gt;
Reviewed-by: Konrad Dybcio &lt;konrad.dybcio@oss.qualcomm.com&gt;
Link: https://lore.kernel.org/r/226c5d1005a6e295e0581b2c89e5510dbb7aa9d1.1772643434.git.geert+renesas@glider.be
Signed-off-by: Bjorn Andersson &lt;andersson@kernel.org&gt;
</content>
</entry>
<entry>
<title>arm64: dts: qcom: sm4450: Add RPMh power domains support</title>
<updated>2025-05-19T20:33:51+00:00</updated>
<author>
<name>Ajit Pandey</name>
<email>quic_ajipan@quicinc.com</email>
</author>
<published>2025-04-17T17:07:41+00:00</published>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/commit/?id=654ac800d4ac6bd4bffa7e98997a1e0d336999b1'/>
<id>urn:sha1:654ac800d4ac6bd4bffa7e98997a1e0d336999b1</id>
<content type='text'>
Add device node for RPMh power domains on Qualcomm SM4450 platform.

Signed-off-by: Ajit Pandey &lt;quic_ajipan@quicinc.com&gt;
Reviewed-by: Dmitry Baryshkov &lt;dmitry.baryshkov@oss.qualcomm.com&gt;
Link: https://lore.kernel.org/r/20250417-sm4450_rpmhpd-v1-3-361846750d3a@quicinc.com
Signed-off-by: Bjorn Andersson &lt;andersson@kernel.org&gt;
</content>
</entry>
<entry>
<title>arm64: dts: qcom: sm4450: correct sleep clock frequency</title>
<updated>2024-12-27T03:51:10+00:00</updated>
<author>
<name>Dmitry Baryshkov</name>
<email>dmitry.baryshkov@linaro.org</email>
</author>
<published>2024-12-24T10:17:09+00:00</published>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/commit/?id=158e67cf3619dbb5b9914bb364889041f4b90eea'/>
<id>urn:sha1:158e67cf3619dbb5b9914bb364889041f4b90eea</id>
<content type='text'>
The SM4450 platform uses PM4450 to provide sleep clock. According to the
documentation, that clock has 32.7645 kHz frequency. Correct the sleep
clock definition.

Fixes: 7a1fd03e7410 ("arm64: dts: qcom: Adds base SM4450 DTSI")
Signed-off-by: Dmitry Baryshkov &lt;dmitry.baryshkov@linaro.org&gt;
Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-10-e9b08fbeadd3@linaro.org
Signed-off-by: Bjorn Andersson &lt;andersson@kernel.org&gt;
</content>
</entry>
<entry>
<title>arm64: dts: qcom: sm: change labels to lower-case</title>
<updated>2024-10-23T00:14:34+00:00</updated>
<author>
<name>Krzysztof Kozlowski</name>
<email>krzysztof.kozlowski@linaro.org</email>
</author>
<published>2024-10-22T15:47:40+00:00</published>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/commit/?id=7b52cb20183de74f8ef7503180c11aa07b015881'/>
<id>urn:sha1:7b52cb20183de74f8ef7503180c11aa07b015881</id>
<content type='text'>
DTS coding style expects labels to be lowercase.  No functional impact.
Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff).

Signed-off-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
Link: https://lore.kernel.org/r/20241022-dts-qcom-label-v3-15-0505bc7d2c56@linaro.org
Signed-off-by: Bjorn Andersson &lt;andersson@kernel.org&gt;
</content>
</entry>
<entry>
<title>arm64: dts: qcom: sm4450: add camera, display and gpu clock controller</title>
<updated>2024-08-15T02:07:04+00:00</updated>
<author>
<name>Ajit Pandey</name>
<email>quic_ajipan@quicinc.com</email>
</author>
<published>2024-06-11T13:37:52+00:00</published>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/commit/?id=b87b8df9c0e4f56e480ef1519140419ea063c9ca'/>
<id>urn:sha1:b87b8df9c0e4f56e480ef1519140419ea063c9ca</id>
<content type='text'>
Add device node for camera, display and graphics clock controller on
Qualcomm SM4450 platform.

Signed-off-by: Ajit Pandey &lt;quic_ajipan@quicinc.com&gt;
Reviewed-by: Dmitry Baryshkov &lt;dmitry.baryshkov@linaro.org&gt;
Link: https://lore.kernel.org/r/20240611133752.2192401-9-quic_ajipan@quicinc.com
Signed-off-by: Bjorn Andersson &lt;andersson@kernel.org&gt;
</content>
</entry>
<entry>
<title>arm64: dts: qcom: Split PMU nodes for heterogeneous CPUs</title>
<updated>2024-05-28T21:07:35+00:00</updated>
<author>
<name>Rob Herring (Arm)</name>
<email>robh@kernel.org</email>
</author>
<published>2024-04-17T20:42:46+00:00</published>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/commit/?id=c8a346e408cb2e516472658ff191f13626d8571e'/>
<id>urn:sha1:c8a346e408cb2e516472658ff191f13626d8571e</id>
<content type='text'>
Arm heterogeneous configurations should have separate PMU nodes for each
CPU uarch as the uarch specific events can be different. The
"arm,armv8-pmuv3" compatible is also intended for s/w models rather than
specific uarch implementations.

All the kryo CPUs are missing PMU compatibles, so they can't be fixed.

Signed-off-by: "Rob Herring (Arm)" &lt;robh@kernel.org&gt;
Link: https://lore.kernel.org/r/20240417204247.3216703-1-robh@kernel.org
Signed-off-by: Bjorn Andersson &lt;andersson@kernel.org&gt;
</content>
</entry>
<entry>
<title>arm64: dts: qcom: sm4450: Add cpufreq support</title>
<updated>2024-05-27T00:10:34+00:00</updated>
<author>
<name>Tengfei Fan</name>
<email>quic_tengfan@quicinc.com</email>
</author>
<published>2024-04-24T10:15:02+00:00</published>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/commit/?id=15476ccd3dc6cea04048d159115c86a3d5042501'/>
<id>urn:sha1:15476ccd3dc6cea04048d159115c86a3d5042501</id>
<content type='text'>
Add a description of a SM4450 cpufreq-epss controller,add references to
it from CPU nodes and make EPSS a supplyer of clocks for the CPUs.

Signed-off-by: Tengfei Fan &lt;quic_tengfan@quicinc.com&gt;
Reviewed-by: Dmitry Baryshkov &lt;dmitry.baryshkov@linaro.org&gt;
Link: https://lore.kernel.org/r/20240424101503.635364-3-quic_tengfan@quicinc.com
Link: https://lore.kernel.org/r/20240424101503.635364-4-quic_tengfan@quicinc.com
[bjorn: Squashed the two changes, and updated commit message]
Signed-off-by: Bjorn Andersson &lt;andersson@kernel.org&gt;
</content>
</entry>
<entry>
<title>arm64: dts: qcom: minor whitespace cleanup</title>
<updated>2024-02-14T15:41:27+00:00</updated>
<author>
<name>Krzysztof Kozlowski</name>
<email>krzysztof.kozlowski@linaro.org</email>
</author>
<published>2024-02-08T10:52:08+00:00</published>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/commit/?id=77e7257a601743a1cd67fa474288389fffa8839e'/>
<id>urn:sha1:77e7257a601743a1cd67fa474288389fffa8839e</id>
<content type='text'>
The DTS code coding style expects exactly one space before '{' and
around '=' characters.

Signed-off-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
Reviewed-by: Dmitry Baryshkov &lt;dmitry.baryshkov@linaro.org&gt;
Link: https://lore.kernel.org/r/20240208105208.128706-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson &lt;andersson@kernel.org&gt;
</content>
</entry>
<entry>
<title>arm64: dts: qcom: sm4450: add uart console support</title>
<updated>2023-12-03T01:33:22+00:00</updated>
<author>
<name>Tengfei Fan</name>
<email>quic_tengfan@quicinc.com</email>
</author>
<published>2023-11-29T10:33:22+00:00</published>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/commit/?id=980679261b061da92fc441fa4e2fdb7ef8baadb2'/>
<id>urn:sha1:980679261b061da92fc441fa4e2fdb7ef8baadb2</id>
<content type='text'>
Add base description of UART and TLMM nodes which helps SM4450
boot to shell with console on boards with this SoC.

Reviewed-by: Konrad Dybcio &lt;konrad.dybcio@linaro.org&gt;
Signed-off-by: Tengfei Fan &lt;quic_tengfan@quicinc.com&gt;
Link: https://lore.kernel.org/r/20231129103325.24854-4-quic_tengfan@quicinc.com
Signed-off-by: Bjorn Andersson &lt;andersson@kernel.org&gt;
</content>
</entry>
<entry>
<title>arm64: dts: qcom: sm4450: Add RPMH and Global clock</title>
<updated>2023-12-03T01:32:53+00:00</updated>
<author>
<name>Tengfei Fan</name>
<email>quic_tengfan@quicinc.com</email>
</author>
<published>2023-11-29T10:33:21+00:00</published>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/commit/?id=483fa5552d352f3bfe835a3156e6cf037c4cf77f'/>
<id>urn:sha1:483fa5552d352f3bfe835a3156e6cf037c4cf77f</id>
<content type='text'>
Add device node for RPMH and Global clock controller on Qualcomm
SM4450 platform.

Reviewed-by: Konrad Dybcio &lt;konrad.dybcio@linaro.org&gt;
Signed-off-by: Ajit Pandey &lt;quic_ajipan@quicinc.com&gt;
Signed-off-by: Tengfei Fan &lt;quic_tengfan@quicinc.com&gt;
Link: https://lore.kernel.org/r/20231129103325.24854-3-quic_tengfan@quicinc.com
Signed-off-by: Bjorn Andersson &lt;andersson@kernel.org&gt;
</content>
</entry>
</feed>
