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<title>lwn.git/arch/arm64/boot/dts/qcom/sc7180.dtsi, branch v5.10-rc5</title>
<subtitle>Linux kernel documentation tree maintained by Jonathan Corbet</subtitle>
<id>http://mirrors.hust.edu.cn/git/lwn.git/atom?h=v5.10-rc5</id>
<link rel='self' href='http://mirrors.hust.edu.cn/git/lwn.git/atom?h=v5.10-rc5'/>
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<updated>2020-09-15T22:33:53+00:00</updated>
<entry>
<title>arm64: dts: qcom: sc7180: Increase the number of interconnect cells</title>
<updated>2020-09-15T22:33:53+00:00</updated>
<author>
<name>Sibi Sankar</name>
<email>sibis@codeaurora.org</email>
</author>
<published>2020-09-03T13:31:34+00:00</published>
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<id>urn:sha1:e23b1220a24600c7b165f4da4eff3519c2eb8167</id>
<content type='text'>
Increase the number of interconnect-cells, as now we can include
the tag information. The consumers can specify the path tag as an
additional argument to the endpoints.

Signed-off-by: Sibi Sankar &lt;sibis@codeaurora.org&gt;
Tested-by: Matthias Kaehlcke &lt;mka@chromium.org&gt;
Reviewed-by: Matthias Kaehlcke &lt;mka@chromium.org&gt;
Signed-off-by: Georgi Djakov &lt;georgi.djakov@linaro.org&gt;
Link: https://lore.kernel.org/r/20200903133134.17201-8-georgi.djakov@linaro.org
Signed-off-by: Bjorn Andersson &lt;bjorn.andersson@linaro.org&gt;
</content>
</entry>
<entry>
<title>arm64: dts: qcom: sc7180: Drop flags on mdss irqs</title>
<updated>2020-09-14T00:04:52+00:00</updated>
<author>
<name>Stephen Boyd</name>
<email>swboyd@chromium.org</email>
</author>
<published>2020-08-11T19:25:03+00:00</published>
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<id>urn:sha1:51e9874d382e089f664b3ce12773bbbaece5f369</id>
<content type='text'>
The number of interrupt cells for the mdss interrupt controller is 1,
meaning there should only be one cell for the interrupt number, not two
where the second cell is the irq flags. Drop the second cell to match
the binding.

Cc: Kalyan Thota &lt;kalyan_t@codeaurora.org&gt;
Cc: Harigovindan P &lt;harigovi@codeaurora.org
Fixes: a3db7ad1af49 ("arm64: dts: sc7180: add display dt nodes")
Signed-off-by: Stephen Boyd &lt;swboyd@chromium.org&gt;
Link: https://lore.kernel.org/r/20200811192503.1811462-1-swboyd@chromium.org
Signed-off-by: Bjorn Andersson &lt;bjorn.andersson@linaro.org&gt;
</content>
</entry>
<entry>
<title>arm64: dts: sc7180: add bus clock to mdp node for sc7180 target</title>
<updated>2020-09-10T22:30:51+00:00</updated>
<author>
<name>Krishna Manikandan</name>
<email>mkrishn@codeaurora.org</email>
</author>
<published>2020-07-16T11:35:33+00:00</published>
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<id>urn:sha1:0a4fd091cf11203c3f0415be85c70daf8db0bd4f</id>
<content type='text'>
Move the bus clock to mdp device node,in order
to facilitate bus band width scaling on sc7180
target.

The parent device MDSS will not vote for bus bw,
instead the vote will be triggered by mdp device
node. Since a minimum vote is required to turn
on bus clock, move the clock node to mdp device
from where the votes are requested.

This patch has dependency on the below series
https://patchwork.kernel.org/patch/11468783/

Reviewed-by: Rob Clark &lt;robdclark@chromium.org&gt;
Signed-off-by: Krishna Manikandan &lt;mkrishn@codeaurora.org&gt;
Link: https://lore.kernel.org/r/1594899334-19772-2-git-send-email-kalyan_t@codeaurora.org
Signed-off-by: Bjorn Andersson &lt;bjorn.andersson@linaro.org&gt;
</content>
</entry>
<entry>
<title>arm64: dts: qcom: sc7180: Add bandwidth votes for eMMC and SDcard</title>
<updated>2020-09-10T22:28:06+00:00</updated>
<author>
<name>Pradeep P V K</name>
<email>ppvk@codeaurora.org</email>
</author>
<published>2020-08-17T06:41:04+00:00</published>
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<id>urn:sha1:fa8da06628626531cda3a008223d99109cbd1f02</id>
<content type='text'>
Add the bandwidth domain supporting performance state and
the corresponding OPP tables for the sdhc device on sc7180.

Signed-off-by: Pradeep P V K &lt;ppvk@codeaurora.org&gt;
Signed-off-by: Shaik Sajida Bhanu &lt;sbhanu@codeaurora.org&gt;
Link: https://lore.kernel.org/r/1597646464-1863-1-git-send-email-sbhanu@codeaurora.org
Signed-off-by: Bjorn Andersson &lt;bjorn.andersson@linaro.org&gt;
</content>
</entry>
<entry>
<title>arm64: dts: qcom: sc7180: Add 'sustainable_power' for CPU thermal zones</title>
<updated>2020-09-10T22:10:03+00:00</updated>
<author>
<name>Matthias Kaehlcke</name>
<email>mka@chromium.org</email>
</author>
<published>2020-08-13T18:30:33+00:00</published>
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<id>urn:sha1:5a4d9f3e18f5e2281f50e7f644e1f9a1589d900b</id>
<content type='text'>
The 'sustainable_power' attribute provides an estimate of the sustained
power that can be dissipated at the desired control temperature. One
could argue that this value is not necessarily the same for all devices
with the same SoC, which may have different form factors or thermal
designs. However there are reasons to specify a (default) value at SoC
level for SC7180: most importantly, if no value is specified at all the
power_allocator thermal governor (aka 'IPA') estimates a value, using the
minimum power of all cooling devices of the zone, which can result in
overly aggressive thermal throttling. For most devices an approximate
conservative value should be more useful than the minimum guesstimate
of power_allocator. Devices that need a different value can overwrite
it in their &lt;device&gt;.dts. Also the thermal zones for SC7180 have a high
level of granularity (essentially one for each function block), which
makes it more likely that the default value just works for many devices.

The values correspond to 1901 MHz for the big cores, and 1804 MHz for
the small cores. The values were determined by limiting the CPU
frequencies to different max values and launching a bunch of processes
that cause high CPU load ('while true; do true; done &amp;' is simple and
does a good job). A frequency is deemed sustainable if the CPU
temperatures don't rise (consistently) above the second trip point
('control temperature', 95 degC in this case). Once the highest
sustainable frequency is found, the sustainable power can be calculated
by multiplying the energy consumption per core at this frequency (which
can be found in /sys/kernel/debug/energy_model/) with the number of
cores that are specified as cooling devices.

The sustainable frequencies were determined at room temperature
on a device without heat sink or other passive cooling elements.

Reviewed-by: Douglas Anderson &lt;dianders@chromium.org&gt;
Signed-off-by: Matthias Kaehlcke &lt;mka@chromium.org&gt;
Link: https://lore.kernel.org/r/20200813113030.1.I89c33c4119eaffb986b1e8c1bc6f0e30267089cd@changeid
Signed-off-by: Bjorn Andersson &lt;bjorn.andersson@linaro.org&gt;
</content>
</entry>
<entry>
<title>arm64: dts: qcom: sc7180: Add OPP tables and power-domains for venus</title>
<updated>2020-09-10T22:03:16+00:00</updated>
<author>
<name>Rajendra Nayak</name>
<email>rnayak@codeaurora.org</email>
</author>
<published>2020-09-01T14:20:26+00:00</published>
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<id>urn:sha1:ef8e58f837e6f5659ca8dc2c49dfe3eaf17a02e1</id>
<content type='text'>
Add the OPP tables in order to be able to vote on the performance state
of a power-domain

Signed-off-by: Rajendra Nayak &lt;rnayak@codeaurora.org&gt;
Link: https://lore.kernel.org/r/1598970026-7199-6-git-send-email-rnayak@codeaurora.org
Signed-off-by: Bjorn Andersson &lt;bjorn.andersson@linaro.org&gt;
</content>
</entry>
<entry>
<title>arm64: dts: qcom: sc7180: add interconnect bindings for display</title>
<updated>2020-09-10T21:42:59+00:00</updated>
<author>
<name>Krishna Manikandan</name>
<email>mkrishn@codeaurora.org</email>
</author>
<published>2020-07-16T11:35:32+00:00</published>
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<id>urn:sha1:81921a37145e0c6581ab913129c3c2a604704eee</id>
<content type='text'>
This change adds the interconnect bindings to the
MDSS node. This will establish Display to DDR path
for bus bandwidth voting.

Reviewed-by: Rob Clark &lt;robdclark@chromium.org&gt;
Signed-off-by: Krishna Manikandan &lt;mkrishn@codeaurora.org&gt;
Link: https://lore.kernel.org/r/1594899334-19772-1-git-send-email-kalyan_t@codeaurora.org
Signed-off-by: Bjorn Andersson &lt;bjorn.andersson@linaro.org&gt;
</content>
</entry>
<entry>
<title>arm64: dts: qcom: sc7180: Add LPASS clock controller nodes</title>
<updated>2020-09-10T16:58:02+00:00</updated>
<author>
<name>Taniya Das</name>
<email>tdas@codeaurora.org</email>
</author>
<published>2020-08-01T18:13:35+00:00</published>
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<id>urn:sha1:f05f2c21187a58753e3754c27cf48f72610b37db</id>
<content type='text'>
Update the clock controller nodes for Low power audio subsystem
functionality.

Reviewed-by: Douglas Anderson &lt;dianders@chromium.org&gt;
Signed-off-by: Taniya Das &lt;tdas@codeaurora.org&gt;
Link: https://lore.kernel.org/r/1596305615-5894-2-git-send-email-tdas@codeaurora.org
Signed-off-by: Bjorn Andersson &lt;bjorn.andersson@linaro.org&gt;
</content>
</entry>
<entry>
<title>arm64: dts: qcom: sc7180: Fix the LLCC base register size</title>
<updated>2020-08-30T17:24:30+00:00</updated>
<author>
<name>Sai Prakash Ranjan</name>
<email>saiprakash.ranjan@codeaurora.org</email>
</author>
<published>2020-08-18T14:55:14+00:00</published>
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<id>urn:sha1:efe788361f72914017515223414d3f20abe4b403</id>
<content type='text'>
There is one LLCC logical bank(LLCC0) on SC7180 SoC and the
size of the LLCC0 base is 0x50000(320KB) not 2MB, so correct
the size and fix copy paste mistake carried over from SDM845.

Reviewed-by: Douglas Anderson &lt;dianders@chromium.org&gt;
Fixes: 7cee5c742899 ("arm64: dts: qcom: sc7180: Fix node order")
Fixes: c831fa299996 ("arm64: dts: qcom: sc7180: Add Last level cache controller node")
Signed-off-by: Sai Prakash Ranjan &lt;saiprakash.ranjan@codeaurora.org&gt;
Link: https://lore.kernel.org/r/20200818145514.16262-1-saiprakash.ranjan@codeaurora.org
Signed-off-by: Bjorn Andersson &lt;bjorn.andersson@linaro.org&gt;
</content>
</entry>
<entry>
<title>arm64: dts: qcom: sc7180: Add DisplayPort HPD pin dt node</title>
<updated>2020-08-30T17:21:29+00:00</updated>
<author>
<name>Tanmay Shah</name>
<email>tanmay@codeaurora.org</email>
</author>
<published>2020-08-18T03:36:57+00:00</published>
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<id>urn:sha1:681a607ad21a4db5877e6287f666ba3622ca84cf</id>
<content type='text'>
This node defines alternate DP HPD functionality of GPIO.

Reviewed-by: Stephen Boyd &lt;swboyd@chromium.org&gt;
Signed-off-by: Tanmay Shah &lt;tanmay@codeaurora.org&gt;
Link: https://lore.kernel.org/r/20200818033657.16074-1-tanmay@codeaurora.org
Signed-off-by: Bjorn Andersson &lt;bjorn.andersson@linaro.org&gt;
</content>
</entry>
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