lwn.git/arch/arm64/boot/dts/qcom/hamoa.dtsi, branch master

Merge tag 'soc-dt-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

2026-04-17T03:28:48+00:00

Pull SoC devicetree updates from Arnd Bergmann: "A number of SoC platforms are adding modernized variants of their already supported chips time, with a total of 12 new SoCs, and two older SoC getting removed: - Qualcomm Glymur is a compute SoC using 18 Oryon-2 CPU cores - Qualcomm Mahua is a variant of Glymur with only 12 CPU cores, but largely identical. - Qualcomm Eliza is an embeded platform for mobile phone (SM7750) and IOT (QC7790S/M) workloads - Qualcomm IPQ5210 is a wireless networking SoC using Cortex-A53 cores - Qualcomm apq8084 and ipq806x had only rudimentary support but no actual products using them, so they are now gone. - Axis ARTPEC-9 is a follow-up to the ARTPEC-8 embedded SoC, using the Samsung SoC platform but now with Cortex-A55 cores - ARM Zena is a virtual platform in FVP using Cortex-A720AE cores, with additional versions planned to be merged in the future. - ARM corstone-1000-a320 is a reference platform for IOT, using low-end Cortex-A320 cores - Microchip LAN9691 is an updated 64-bit variant of the arm32 lan966x series of networking SoCs - Microchip PIC64GX is an embedded RISC-V chip using SIFIVE U54 CPU cores - Rockchip RV1103B is the low-end 32-bit single-core vision processor - Renesas RZ/G3L (r9a08g046) is an industrial embedded chip using Cortex-A55 cores, similar to the G3E and G3S variants we already supported. - NXP S32N79 is an automotive SoC using Cortex-A78AE cores, a significant upgrade from the older S32V and S32G series These all come with at least one reference board or an initial product using these, in total there are 67 newly added boards. The ones for already supported SoCs are: - Two more Aspeed BMC based boards - Three older tablets based on 32-bit OMAP4 and Exynos5 SoCs - One Set-top-box based on Allwinner H6 - 22 additional industrial/embedded boards using 64-bit NXP i.MX8M or i.MX9 SoCs - 20 Qualcomm SoC based machines across all possible markets: workstation, gaming, laptop, phone, networking, reference, ... - Three more Rockchips rk35xx based boards - Four variants of the Toradex Verdin using TI AM62 Other notable bits are: - A cleanup for the 32-bit Tegra paz00 board moved the last board specific code on Tegra into equivalent dts syntax. - There continues to be a significant number of fixes for static checking of dtc syntax, but it feels like this is slowing down, hopefully getting into a state where most known issues are addressed - Additional hardware support for many existing boards across SoC families, notably Qualcomm, Broadcom, i.MX2, i.MX6, Rockchips, STM32, Mediatek, Tegra, TI and Microchip" * tag 'soc-dt-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (841 commits) arm64: dts: ti: k3: Use memory-region-names for r5f ARM: dts: imx: Add DT overlays for DH i.MX6 DHCOM SoM and boards ARM: dts: imx6sx: remove fallback compatible string fsl,imx28-lcdif ARM: dts: imx25: rename node name tcq to touchscreen ARM: dts: imx: b850v3: Disable unused usdhc4 ARM: dts: imx: b850v3: Define GPIO line names ARM: dts: imx: b850v3: Use alphabetical sorting ARM: dts: imx: bx50v3: Configure phy-mode to eliminate a warning ARM: dts: imx: bx50v3: Configure switch PHY max-speed to 100Mbps ARM: dts: imx7ulp: Add CPU clock and OPP table support ARM: dts: imx7-mba7: Deassert BOOT_EN after boot ARM: dts: tqma7: add boot phase properties ARM: dts: imx7s: add boot phase properties ARM: dts: tqma6ul[l]: correct spelling of TQ-Systems ARM: dts: mba6ulx: add boot phase properties ARM: dts: imx6ul[l]-tqma6ul[l]: add boot phase properties ARM: dts: imx6ul/imx6ull: add boot phase properties ARM: dts: imx6qdl-mba6: add boot phase properties ARM: dts: imx6qdl-tqma6: add boot phase properties ARM: dts: imx6qdl: add boot phase properties ...

arm64: dts: qcom: purwa: deduplicate thermal sensors with Hamoa

2026-03-26T14:40:58+00:00

Hamoa and Purwa have pretty close thermal zones definitions. The major difference is that several zones are absent (because of the lack of the CPU cluster) and several zones use tsens2 instead of tsens3. Instead of completely duplicating thermal zones for Purwa, reuse themal zones from Hamoa, patching them where required. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20260320-purwa-drop-thermals-v1-1-2c9fe046cd02@oss.qualcomm.com Signed-off-by: Bjorn Andersson

arm64: dts: qcom: hamoa/purwa: Flatten usb controller nodes

2026-03-26T14:40:49+00:00

Flatten usb controller nodes and update to using latest bindings and flattened driver approach. Tested this patch on CRD platform. For testing purpose, modified dr_mode property and added usb-role-switch property to the 3 super speed capable DRD controllers and valdiated both host and device mode. Also validated host mode on the multiport controller. Signed-off-by: Krishna Kurapati Link: https://lore.kernel.org/r/20260323103119.1801139-1-krishna.kurapati@oss.qualcomm.com Signed-off-by: Bjorn Andersson

arm64: dts: qcom: hamoa: Add UFS nodes for x1e80100 SoC

2026-03-26T14:40:44+00:00

Add UFS host controller and PHY nodes for x1e80100 SoC. Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa Reviewed-by: Taniya Das Reviewed-by: Manivannan Sadhasivam Signed-off-by: Pradeep P V K Link: https://lore.kernel.org/r/20260211132926.3716716-3-pradeep.pragallapati@oss.qualcomm.com Signed-off-by: Bjorn Andersson

arm64: dts: qcom: hamoa: Fix xo clock supply of platform SD host controller

2026-03-26T14:40:41+00:00

The expected frequency of SD host controller core supply clock is 19.2MHz, while RPMH_CXO_CLK clock frequency on SM8650 platform is 38.4MHz. Apparently the overclocked supply clock could be good enough on some boards and even with the most of SD cards, however some low-end UHS-I SD cards in SDR104 mode of the host controller produce I/O errors in runtime, fortunately this problem is gone, if the "xo" clock frequency matches the expected 19.2MHz clock rate. Fixes: ffb21c1e19b1 ("arm64: dts: qcom: x1e80100: Describe the SDHC controllers") Reported-by: Neil Armstrong Signed-off-by: Vladimir Zapolskiy Reviewed-by: Konrad Dybcio Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20260314023715.357512-4-vladimir.zapolskiy@linaro.org Signed-off-by: Bjorn Andersson

arm64: dts: qcom: hamoa: correct Iris corners for the MXC rail

2026-03-26T14:40:38+00:00

The corners of the MVS0 / MVS0C clocks on the MMCX rail don't always match the PLL corners on the MXC rail. Correct the performance corners for the MXC rail following the PLL documentation. Fixes: 9065340ac04d ("arm64: dts: qcom: x1e80100: Add IRIS video codec") Signed-off-by: Dmitry Baryshkov Reviewed-by: Dikshita Agarwal Link: https://lore.kernel.org/r/20260313-iris-fix-corners-v1-1-32a393c25dda@oss.qualcomm.com Signed-off-by: Bjorn Andersson

arm64: dts: qcom: x1e80100: Add '#cooling-cells' for CPU nodes

2026-03-18T12:16:51+00:00

Enable passive cooling for CPUs in the X1E80100 SoC by adding the '#cooling-cells' property. This will allow the OS to mitigate the CPU power dissipation with the help of SCMI DVFS. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Tested-by: Gaurav Kohli Link: https://lore.kernel.org/r/20260210070321.17033-1-manivannan.sadhasivam@oss.qualcomm.com Signed-off-by: Bjorn Andersson

arm64: dts: qcom: correct RBR opp entry

2026-03-09T23:09:48+00:00

DisplayPort Reduced Bit Rate uses link rate of 1.62 Gbps, the main link clock should be 162 MHz. Having the incorrect frequency (160 MHz) in the OPP table will result in selecting wrong link frequency. Correct the entry in the OPP table. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260304-msm-fix-rbr-v1-1-b9eba986eaef@oss.qualcomm.com Signed-off-by: Bjorn Andersson

arm64: dts: qcom: hamoa/x1: fix idle exit latency

2026-02-23T15:43:56+00:00

Designs based on the Qualcomm X1 Hamoa reference platform report: driver: Idle state 1 target residency too low This is because the declared X1 idle entry plus exit latency of 680us exceeds the declared minimum 600us residency time: entry-latency-us = <180>; exit-latency-us = <500>; min-residency-us = <600>; Fix this to be 320us so the sum of the entry and exit latencies matches the downstream 500us exit latency, as directed by Maulik. Tested on a Lenovo Yoga Slim 7x with Qualcomm X1E-80-100. Fixes: 2e65616ef07f ("arm64: dts: qcom: x1e80100: Update C4/C5 residency/exit numbers") Signed-off-by: Daniel J Blueman Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260220124626.8611-1-daniel@quora.org Signed-off-by: Bjorn Andersson

arm64: dts: qcom: hamoa: Add the APSS watchdog

2026-01-19T19:39:51+00:00

The watchdog support in EL1 is SBSA compliant, handled by Gunyah hypervisor, but in EL2. the watchdog is an instance of the APSS WDT HW block, same as older platforms. So describe the APSS WDT node and mark it as reserved, as it will only be enabled in EL2 overlay. Signed-off-by: Abel Vesa Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251224-arm64-dts-qcom-x1e80100-el2-add-apss-wdt-v3-2-1801c55d2883@oss.qualcomm.com Signed-off-by: Bjorn Andersson