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<title>lwn.git/arch/arm/mach-tegra/fuse.h, branch docs-5.8-2</title>
<subtitle>Linux kernel documentation tree maintained by Jonathan Corbet</subtitle>
<id>http://mirrors.hust.edu.cn/git/lwn.git/atom?h=docs-5.8-2</id>
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<updated>2014-07-17T12:36:01+00:00</updated>
<entry>
<title>soc/tegra: Add efuse driver for Tegra</title>
<updated>2014-07-17T12:36:01+00:00</updated>
<author>
<name>Peter De Schrijver</name>
<email>pdeschrijver@nvidia.com</email>
</author>
<published>2014-06-12T15:36:37+00:00</published>
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<id>urn:sha1:783c8f4c84451bc444e314a71b447239c6ef6fd9</id>
<content type='text'>
Implement fuse driver for Tegra20, Tegra30, Tegra114 and Tegra124. This
replaces functionality previously provided in arch/arm/mach-tegra, which
is removed in this patch.

While at it, move the only user of the global tegra_revision variable
over to tegra_sku_info.revision and export tegra_fuse_readl() to allow
drivers to read calibration fuses.

Signed-off-by: Peter De Schrijver &lt;pdeschrijver@nvidia.com&gt;
Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>ARM: tegra: move fuse exports to soc/tegra/fuse.h</title>
<updated>2014-07-17T12:32:51+00:00</updated>
<author>
<name>Peter De Schrijver</name>
<email>pdeschrijver@nvidia.com</email>
</author>
<published>2014-06-12T15:36:36+00:00</published>
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<id>urn:sha1:35874f3617b38e0c1f72163407c41d554a8f5939</id>
<content type='text'>
All fuse related functionality will move to a driver in the following
patches. To prepare for this, export all the required functionality in a
global header file and move all users of fuse.h to soc/tegra/fuse.h.

While we're at it, remove tegra_bct_strapping, as its only user was
removed in Commit a7cbe92cef27 ("ARM: tegra: remove tegra EMC scaling
driver").

Signed-off-by: Peter De Schrijver &lt;pdeschrijver@nvidia.com&gt;
Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>ARM: tegra: Use a function to get the chip ID</title>
<updated>2014-07-17T11:36:41+00:00</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2014-07-11T07:52:41+00:00</published>
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<id>urn:sha1:304664eab93f9e95a8d28fbd9702ede88bb10cc5</id>
<content type='text'>
Instead of using a simple variable access to get at the Tegra chip ID,
use a function so that we can run additional code. This can be used to
determine where the chip ID is being accessed without being available.
That in turn will be handy for resolving boot sequence dependencies in
order to convert more code to regular initcalls rather than a sequence
fixed by Tegra SoC setup code.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>ARM: tegra: add Tegra124 SoC support</title>
<updated>2013-10-18T22:28:07+00:00</updated>
<author>
<name>Joseph Lo</name>
<email>josephl@nvidia.com</email>
</author>
<published>2013-10-08T04:50:03+00:00</published>
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<id>urn:sha1:7394447505c466d1b5cc664dcec5b2b68aa59142</id>
<content type='text'>
Add Tegra124 SoC support that base on CortexA15MP Core. And enable the
SMP function that can re-use the same procedure with Tegra114.

Signed-off-by: Joseph Lo &lt;josephl@nvidia.com&gt;
Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>ARM: tegra: add an assembly marco to check Tegra SoC ID</title>
<updated>2013-05-22T21:19:21+00:00</updated>
<author>
<name>Joseph Lo</name>
<email>josephl@nvidia.com</email>
</author>
<published>2013-05-20T10:39:24+00:00</published>
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<id>urn:sha1:4b3e2edacf4344cdf7863b6fae64ccb8b02fe9f5</id>
<content type='text'>
There are some Tegra SoC ID checking code around the low level assembly
code. Adding a marco to replace them. For the single image to support all
the Tegra series, we may also need the marco in other common code. So we
make it become a marco for the usage.

Signed-off-by: Joseph Lo &lt;josephl@nvidia.com&gt;
Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>ARM: tegra: add speedo-based process id for Tegra114</title>
<updated>2013-03-19T17:52:06+00:00</updated>
<author>
<name>Danny Huang</name>
<email>dahuang@nvidia.com</email>
</author>
<published>2013-03-18T11:17:34+00:00</published>
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<id>urn:sha1:7495b2eb0770b85e58af98b99faaf853e9563784</id>
<content type='text'>
Add speedo-based process identification for Tegra114.

Based on the work by: Alex Frid &lt;afrid@nvidia.com&gt;

Signed-off-by: Danny Huang &lt;dahuang@nvidia.com&gt;
[swarren: added include of bug.h]
Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>ARM: tegra: fuse: Add chip ID Tegra114 0x35</title>
<updated>2013-01-28T18:23:00+00:00</updated>
<author>
<name>Hiroshi Doyu</name>
<email>hdoyu@nvidia.com</email>
</author>
<published>2013-01-24T01:10:22+00:00</published>
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<id>urn:sha1:7b30d4578a4ceb9ea3f5c3d999dfe6159092c4a0</id>
<content type='text'>
Add tegra_chip_id TEGRA114 0x35

Signed-off-by: Hiroshi Doyu &lt;hdoyu@nvidia.com&gt;
Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>ARM: tegra: Tegra30 speedo-based process identification</title>
<updated>2012-11-15T21:36:59+00:00</updated>
<author>
<name>Danny Huang</name>
<email>dahuang@nvidia.com</email>
</author>
<published>2012-11-15T07:42:34+00:00</published>
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<id>urn:sha1:f8ddda713b9ea6c10012429c089c81bc9a5cd49f</id>
<content type='text'>
This patch adds speedo-based process identification support for Tegra30.

Signed-off-by: Danny Huang &lt;dahuang@nvidia.com&gt;
[swarren s/Tegra3/Tegra30/ in log print,
s/T30/Tegra30/ in commit description]
Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>ARM: tegra: Add speedo-based process identification</title>
<updated>2012-11-15T21:34:20+00:00</updated>
<author>
<name>Danny Huang</name>
<email>dahuang@nvidia.com</email>
</author>
<published>2012-11-15T07:42:33+00:00</published>
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<id>urn:sha1:25cd5a391478b1e29ef7de172b3bd612159a07cc</id>
<content type='text'>
Detect CPU and core process ID by checking speedo corner tables.
This can provide a more accurate process ID.

Signed-off-by: Danny Huang &lt;dahuang@nvidia.com&gt;
[swarren s/Tegra2/Tegra20/ in log print]
Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>ARM: tegra: flexible spare fuse read function</title>
<updated>2012-11-15T21:16:46+00:00</updated>
<author>
<name>Danny Huang</name>
<email>dahuang@nvidia.com</email>
</author>
<published>2012-11-15T07:42:32+00:00</published>
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<id>urn:sha1:1f851a262baf7cbd4096d4d279c73cb697021773</id>
<content type='text'>
Change the spare fuse base from a definition to a variable.
It provides flexibilty to read spare fuse on different chip.

Signed-off-by: Danny Huang &lt;dahuang@nvidia.com&gt;
Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
</content>
</entry>
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