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<title>lwn.git/arch/arm/mach-davinci/sleep.S, branch docs-fixes</title>
<subtitle>Linux kernel documentation tree maintained by Jonathan Corbet</subtitle>
<id>http://mirrors.hust.edu.cn/git/lwn.git/atom?h=docs-fixes</id>
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<updated>2020-07-21T14:51:33+00:00</updated>
<entry>
<title>ARM: davinci: Replace HTTP links with HTTPS ones</title>
<updated>2020-07-21T14:51:33+00:00</updated>
<author>
<name>Alexander A. Klimov</name>
<email>grandmaster@al2klimov.de</email>
</author>
<published>2020-07-19T10:20:20+00:00</published>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/commit/?id=fb01eb36518f525a6b4e8d829e1127e6a82d7623'/>
<id>urn:sha1:fb01eb36518f525a6b4e8d829e1127e6a82d7623</id>
<content type='text'>
Rationale:
Reduces attack surface on kernel devs opening the links for MITM
as HTTPS traffic is much harder to manipulate.

Deterministic algorithm:
For each file:
  If not .svg:
    For each line:
      If doesn't contain `\bxmlns\b`:
        For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`:
	  If neither `\bgnu\.org/license`, nor `\bmozilla\.org/MPL\b`:
            If both the HTTP and HTTPS versions
            return 200 OK and serve the same content:
              Replace HTTP with HTTPS.

Signed-off-by: Alexander A. Klimov &lt;grandmaster@al2klimov.de&gt;
[nsekhar@ti.com: drop obsolete hawkboard.org URL completeley
		 fixup subject line prefix]
Signed-off-by: Sekhar Nori &lt;nsekhar@ti.com&gt;
</content>
</entry>
<entry>
<title>ARM: davinci: fix sleep.S build error on ARMv4</title>
<updated>2019-07-23T17:12:53+00:00</updated>
<author>
<name>Arnd Bergmann</name>
<email>arnd@arndb.de</email>
</author>
<published>2019-07-22T14:51:50+00:00</published>
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<id>urn:sha1:d64b212ea960db4276a1d8372bd98cb861dfcbb0</id>
<content type='text'>
When building a multiplatform kernel that includes armv4 support,
the default target CPU does not support the blx instruction,
which leads to a build failure:

arch/arm/mach-davinci/sleep.S: Assembler messages:
arch/arm/mach-davinci/sleep.S:56: Error: selected processor does not support `blx ip' in ARM mode

Add a .arch statement in the sources to make this file build.

Link: https://lore.kernel.org/r/20190722145211.1154785-1-arnd@arndb.de
Acked-by: Sekhar Nori &lt;nsekhar@ti.com&gt;
Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
Signed-off-by: Olof Johansson &lt;olof@lixom.net&gt;
</content>
</entry>
<entry>
<title>treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 333</title>
<updated>2019-06-05T15:37:06+00:00</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2019-05-29T23:57:47+00:00</published>
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<id>urn:sha1:4505153954fdb1465d2b178288a9bf646f2a2166</id>
<content type='text'>
Based on 1 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license version 2 as
  published by the free software foundation this program is
  distributed in the hope that it will be useful but without any
  warranty without even the implied warranty of merchantability or
  fitness for a particular purpose see the gnu general public license
  for more details you should have received a copy of the gnu general
  public license along with this program if not write to the free
  software foundation inc 59 temple place suite 330 boston ma 02111
  1307 usa

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 136 file(s).

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Reviewed-by: Alexios Zavras &lt;alexios.zavras@intel.com&gt;
Reviewed-by: Allison Randal &lt;allison@lohutok.net&gt;
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190530000436.384967451@linutronix.de
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>ARM: davinci: make headers more local</title>
<updated>2015-12-01T20:52:51+00:00</updated>
<author>
<name>Arnd Bergmann</name>
<email>arnd@arndb.de</email>
</author>
<published>2015-01-30T09:45:33+00:00</published>
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<id>urn:sha1:3acf731ccad039d91721b6cd9fc85569e9f958ca</id>
<content type='text'>
Some header files are never included outside of a mach-davinci
directory and do not need to be made visible in include/mach,
so let's just move them all down one level.

Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
Acked-by: Sekhar Nori &lt;nsekhar@ti.com&gt;
</content>
</entry>
<entry>
<title>ARM: convert all "mov.* pc, reg" to "bx reg" for ARMv6+</title>
<updated>2014-07-18T11:29:04+00:00</updated>
<author>
<name>Russell King</name>
<email>rmk+kernel@arm.linux.org.uk</email>
</author>
<published>2014-06-30T15:29:12+00:00</published>
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<id>urn:sha1:6ebbf2ce437b33022d30badd49dc94d33ecfa498</id>
<content type='text'>
ARMv6 and greater introduced a new instruction ("bx") which can be used
to return from function calls.  Recent CPUs perform better when the
"bx lr" instruction is used rather than the "mov pc, lr" instruction,
and this sequence is strongly recommended to be used by the ARM
architecture manual (section A.4.1.1).

We provide a new macro "ret" with all its variants for the condition
code which will resolve to the appropriate instruction.

Rather than doing this piecemeal, and miss some instances, change all
the "mov pc" instances to use the new macro, with the exception of
the "movs" instruction and the kprobes code.  This allows us to detect
the "mov pc, lr" case and fix it up - and also gives us the possibility
of deploying this for other registers depending on the CPU selection.

Reported-by: Will Deacon &lt;will.deacon@arm.com&gt;
Tested-by: Stephen Warren &lt;swarren@nvidia.com&gt; # Tegra Jetson TK1
Tested-by: Robert Jarzmik &lt;robert.jarzmik@free.fr&gt; # mioa701_bootresume.S
Tested-by: Andrew Lunn &lt;andrew@lunn.ch&gt; # Kirkwood
Tested-by: Shawn Guo &lt;shawn.guo@freescale.com&gt;
Tested-by: Tony Lindgren &lt;tony@atomide.com&gt; # OMAPs
Tested-by: Gregory CLEMENT &lt;gregory.clement@free-electrons.com&gt; # Armada XP, 375, 385
Acked-by: Sekhar Nori &lt;nsekhar@ti.com&gt; # DaVinci
Acked-by: Christoffer Dall &lt;christoffer.dall@linaro.org&gt; # kvm/hyp
Acked-by: Haojian Zhuang &lt;haojian.zhuang@gmail.com&gt; # PXA3xx
Acked-by: Stefano Stabellini &lt;stefano.stabellini@eu.citrix.com&gt; # Xen
Tested-by: Uwe Kleine-König &lt;u.kleine-koenig@pengutronix.de&gt; # ARMv7M
Tested-by: Simon Horman &lt;horms+renesas@verge.net.au&gt; # Shmobile
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
</entry>
<entry>
<title>Merge branch 'mach_memory_h' of git://git.linaro.org/people/nico/linux into devel-stable</title>
<updated>2011-10-18T12:40:54+00:00</updated>
<author>
<name>Russell King</name>
<email>rmk+kernel@arm.linux.org.uk</email>
</author>
<published>2011-10-18T12:40:54+00:00</published>
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<id>urn:sha1:cefd3e71efca6f4ef7f06f1fc507771d76072741</id>
<content type='text'>
</content>
</entry>
<entry>
<title>ARM: mach-davinci: remove mach/memory.h</title>
<updated>2011-10-13T16:49:47+00:00</updated>
<author>
<name>Nicolas Pitre</name>
<email>nicolas.pitre@linaro.org</email>
</author>
<published>2011-07-06T02:52:57+00:00</published>
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<id>urn:sha1:0020afb369859472a461ef4af6410732e929d402</id>
<content type='text'>
Move some DDR2 related defines into a private &lt;mach/ddr2.h&gt; beforehand.

Signed-off-by: Nicolas Pitre &lt;nicolas.pitre@linaro.org&gt;
</content>
</entry>
<entry>
<title>ARM: davinci: fix cache flush build error</title>
<updated>2011-09-07T11:52:12+00:00</updated>
<author>
<name>Linus Walleij</name>
<email>linus.walleij@linaro.org</email>
</author>
<published>2011-08-02T15:48:38+00:00</published>
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<id>urn:sha1:897a6a1a14837d6d582bfd1fd7aba00be44b6469</id>
<content type='text'>
The TNET variant of DaVinci compiles some code that it shares
with other DaVinci variants, however it has a V6 CPU rather than
an ARM926T, thus the hardcoded call to arm926_flush_kern_cache_all()
in sleep.S will obviously fail, and we need to build with the
v6_flush_kern_cache_all() call instead. This was triggered by
manually altering the DaVinci config to build the TNET version.

Cc: Dave Martin &lt;dave.martin@linaro.org&gt;
Cc: Arnd Bergmann &lt;arnd@arndb.de&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Signed-off-by: Sekhar Nori &lt;nsekhar@ti.com&gt;
Cc: stable@kernel.org
</content>
</entry>
<entry>
<title>davinci: add power management support</title>
<updated>2010-02-04T21:29:55+00:00</updated>
<author>
<name>Sekhar Nori</name>
<email>nsekhar@ti.com</email>
</author>
<published>2009-12-17T12:59:31+00:00</published>
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<id>urn:sha1:efc1bb8a6fd56f6df5b797dff5156c935175c319</id>
<content type='text'>
This patch adds core power management (suspend-to-RAM)
support for DaVinci SoCs.

The code depends on the the "deepsleep" feature to suspend
the SoC and saves power by gating the input clock.

The wakeup can be based on an external event as supported
by the SoC.

Assembly code (in sleep.S) is added to aid gating DDR2
clocks. Code doing this work should not be accessing DDR2.
The assembly code is relocated to SRAM by the code in pm.c

The support has been validated on DA850/OMAP-L138 only
though the code is (hopefully) generic enough that other
SoCs supporting deepsleep feature simply requires SoC
specific code to start using this driver.

Note that all the device drivers don't support suspend/resume
still and are being worked on.

Signed-off-by: Sekhar Nori &lt;nsekhar@ti.com&gt;
Signed-off-by: Kevin Hilman &lt;khilman@deeprootsystems.com&gt;
</content>
</entry>
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