lwn.git/arch/arc/plat-axs10x, branch docs-5.6

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500

2019-06-19T15:09:55+00:00

Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner Reviewed-by: Enrico Weigelt Reviewed-by: Kate Stewart Reviewed-by: Allison Randal Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174

2019-05-30T18:26:41+00:00

Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 655 file(s). Signed-off-by: Thomas Gleixner Reviewed-by: Allison Randal Reviewed-by: Kate Stewart Reviewed-by: Richard Fontana Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070034.575739538@linutronix.de Signed-off-by: Greg Kroah-Hartman

PCI: consolidate PCI config entry in drivers/pci

2018-11-23T02:45:34+00:00

There is no good reason to duplicate the PCI menu in every architecture. Instead provide a selectable HAVE_PCI symbol that indicates availability of PCI support, and a FORCE_PCI symbol to for PCI on and the handle the rest in drivers/pci. Signed-off-by: Christoph Hellwig Reviewed-by: Palmer Dabbelt Acked-by: Max Filippov Acked-by: Thomas Gleixner Acked-by: Bjorn Helgaas Acked-by: Geert Uytterhoeven Acked-by: Paul Burton Signed-off-by: Masahiro Yamada

ARC: [plat-axs103] refactor the quad core DT quirk code

2017-12-20T20:41:45+00:00

Refactor the quad core DT quirk code: get rid of waste division and multiplication by 1000000 constant. Acked-by: Stephen Boyd Signed-off-by: Eugeniy Paltsev Signed-off-by: Vineet Gupta

ARC: [plat-axs103]: Set initial core pll output frequency

2017-12-20T20:41:45+00:00

Set initial core pll output frequency specified in device tree to 100MHz for SMP configuration and 90MHz for UP configuration. It will be applied at the core pll driver probing. Update platform quirk for decreasing core frequency for quad core configuration. Acked-by: Stephen Boyd Signed-off-by: Eugeniy Paltsev Signed-off-by: Vineet Gupta

ARC: [plat-axs10x] DTS: Add reset controller node to manage ethernet reset

2017-11-15T17:40:43+00:00

DW ethernet controller on axs10x hangs sometimes after SW reset. Invoke the newly aded driver (reset-axs10x.c) by adding the DT bits. With this in place, we don't need the open-coded quirk in platform code, so get rid of it as well ! Signed-off-by: Eugeniy Paltsev Signed-off-by: Vineet Gupta Signed-off-by: Eugeniy Paltsev Signed-off-by: Vineet Gupta

ARC: [plat-axs10x] auto-select AXS101 or AXS103 given the ISA config

2017-10-29T23:19:30+00:00

AXS10x platform has two flavours: - AXS101 (ARC700 cpu, ARCompact ISA) - AXS103 (ARC HS38x cpu, ARCv2 ISA) So depending on the ISA support configured, pre-select the AXS10x variant. Signed-off-by: Vineet Gupta

ARC: [plat-axs103] Add temporary quirk to reset ethernet IP

2017-10-04T03:36:49+00:00

DW ethernet controller on AXS10x hangs sometimes after SW reset, so add temporary quirk to reset DW ethernet controller IP core. This quirk can be removed after axs10x reset driver (see http://patchwork.ozlabs.org/patch/800273/) or simple reset driver (see https://patchwork.kernel.org/patch/9903375/) will be available in upstream. Signed-off-by: Eugeniy Paltsev Signed-off-by: Vineet Gupta

ARC: [plat-axs103] refactor the DT fudging code

2017-09-01T18:26:26+00:00

with clk frequency setting code gone by prev commits, we can elide the unconditonal DT parsing to the specific case of quad core config where we possibly need to fudge the DT value. Signed-off-by: Vineet Gupta

ARC: [plat-axs103] use clk driver #1: Get rid of platform specific cpu clk setting

2017-09-01T18:26:24+00:00

historically axs103 platform code used to set the cpu clk by writing to PLL registers directly. however the axs10x clk driver is now upstream so no need to do this amymore. Driver is selected automatically when CONFIG_ARC_PLAT_AXS10X is set Signed-off-by: Eugeniy Paltsev Signed-off-by: Vineet Gupta [vgupta: deleted more code not needed anymore]