lwn.git/Documentation/devicetree/bindings/net/xilinx_axienet.txt, branch v6.9-rc4

dt-bindings: net: xlnx,axi-ethernet: convert bindings document to yaml

2023-06-12T07:48:24+00:00

Convert the bindings document for Xilinx AXI Ethernet Subsystem from txt to yaml. No changes to existing binding description. Signed-off-by: Radhey Shyam Pandey Signed-off-by: Sarath Babu Naidu Gaddam Signed-off-by: David S. Miller

dt-bindings: describe the support of "clock-frequency" in mdio

2022-11-21T10:36:03+00:00

mdio bus frequency is going to be configurable at boottime by a property in DT now, so add a description to it. Signed-off-by: Andy Chiu Reviewed-by: Greentime Hu Reviewed-by: Andrew Lunn Acked-by: Rob Herring Signed-off-by: David S. Miller

dt-bindings: net: add pcs-handle attribute

2022-04-06T12:54:51+00:00

Document the new pcs-handle attribute to support connecting to an external PHY. For Xilinx's AXI Ethernet, this is used when the core operates in SGMII or 1000Base-X modes and links through the internal PCS/PMA PHY. Signed-off-by: Andy Chiu Reviewed-by: Greentime Hu Reviewed-by: Rob Herring Reviewed-by: Andrew Lunn Signed-off-by: David S. Miller

dt-bindings: net: xilinx_axienet: Document additional clocks

2021-03-26T22:17:17+00:00

Update DT bindings to describe all of the clocks that the axienet driver will now be able to make use of. Acked-by: Rob Herring Signed-off-by: Robert Hancock Reviewed-by: Andrew Lunn Signed-off-by: David S. Miller

dt-bindings: net: xilinx_axienet: add xlnx,switch-x-sgmii attribute

2021-02-13T01:38:53+00:00

Document the new xlnx,switch-x-sgmii attribute which is used to indicate that the Ethernet core supports dynamic switching between 1000BaseX and SGMII. Signed-off-by: Robert Hancock Signed-off-by: David S. Miller

net: axienet: document axistream-connected attribute

2019-06-06T23:24:30+00:00

The axienet driver requires the use of an axistream-connected attribute, but this isn't documented in the devicetree bindings. Document how this attribute is supposed to be used, including the upcoming change to make the usage of this attribute optional. Signed-off-by: Robert Hancock Signed-off-by: David S. Miller

net: axienet: document device tree mdio child node

2019-06-06T23:24:30+00:00

The mdio child node for the MDIO bus is generally required when using this driver but was not documented other than being shown in the example. Document it as an optional (but usually required) parameter. Signed-off-by: Robert Hancock Signed-off-by: David S. Miller

net: axienet: Add optional support for Ethernet core interrupt

2019-06-06T23:24:29+00:00

Previously this driver only handled interrupts from the DMA RX and TX blocks, not from the Ethernet core itself. Add optional support for the Ethernet core interrupt, which is used to detect rx_missed and framing errors signalled by the hardware. In order to use this interrupt, a third interrupt needs to be specified in the device tree. Signed-off-by: Robert Hancock Signed-off-by: David S. Miller

net: axienet: Use clock framework to get device clock rate

2019-06-06T23:24:29+00:00

This driver was previously always calculating the MDIO clock divisor (from AXI bus clock to MDIO bus clock) based on the CPU clock frequency, assuming that it is the same as the AXI bus frequency, but that simplistic method only works on the MicroBlaze platform. Add support for specifying the clock used for the device in the device tree using the clock framework. If the clock is specified then it will be used when calculating the clock divisor. The previous CPU clock detection method is left for backward compatibility if no clock is specified. Signed-off-by: Robert Hancock Signed-off-by: David S. Miller

net: axienet: add support for standard phy-mode binding

2017-07-17T15:51:57+00:00

Keep supporting proprietary "xlnx,phy-type" attribute and add support for MII connectivity to the PHY. Reviewed-by: Andrew Lunn Signed-off-by: Alvaro Gamez Machado Signed-off-by: David S. Miller