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<title>lwn.git/Documentation/arm64/cpu-feature-registers.rst, branch docs-mw</title>
<subtitle>Linux kernel documentation tree maintained by Jonathan Corbet</subtitle>
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<updated>2023-06-21T14:51:51+00:00</updated>
<entry>
<title>docs: arm64: Move arm64 documentation under Documentation/arch/</title>
<updated>2023-06-21T14:51:51+00:00</updated>
<author>
<name>Jonathan Corbet</name>
<email>corbet@lwn.net</email>
</author>
<published>2023-06-12T12:06:39+00:00</published>
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<id>urn:sha1:e4624435f38b34e7ce827070aa0f8b533a37c07e</id>
<content type='text'>
Architecture-specific documentation is being moved into Documentation/arch/
as a way of cleaning up the top-level documentation directory and making
the docs hierarchy more closely match the source hierarchy.  Move
Documentation/arm64 into arch/ (along with the Chinese equvalent
translations) and fix up documentation references.

Cc: Will Deacon &lt;will@kernel.org&gt;
Cc: Alex Shi &lt;alexs@kernel.org&gt;
Cc: Hu Haowen &lt;src.res@email.cn&gt;
Cc: Paolo Bonzini &lt;pbonzini@redhat.com&gt;
Acked-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
Reviewed-by: Yantengsi &lt;siyanteng@loongson.cn&gt;
Signed-off-by: Jonathan Corbet &lt;corbet@lwn.net&gt;
</content>
</entry>
<entry>
<title>arm64: cpufeature: Fix the visibility of compat hwcaps</title>
<updated>2022-11-03T18:04:56+00:00</updated>
<author>
<name>Amit Daniel Kachhap</name>
<email>amit.kachhap@arm.com</email>
</author>
<published>2022-11-03T08:22:32+00:00</published>
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<id>urn:sha1:85f1506337f0c79a4955edfeee86a18628e3735f</id>
<content type='text'>
Commit 237405ebef58 ("arm64: cpufeature: Force HWCAP to be based on the
sysreg visible to user-space") forced the hwcaps to use sanitised
user-space view of the id registers. However, the ID register structures
used to select few compat cpufeatures (vfp, crc32, ...) are masked and
hence such hwcaps do not appear in /proc/cpuinfo anymore for PER_LINUX32
personality.

Add the ID register structures explicitly and set the relevant entry as
visible. As these ID registers are now of type visible so make them
available in 64-bit userspace by making necessary changes in register
emulation logic and documentation.

While at it, update the comment for structure ftr_generic_32bits[] which
lists the ID register that use it.

Fixes: 237405ebef58 ("arm64: cpufeature: Force HWCAP to be based on the sysreg visible to user-space")
Cc: Suzuki K Poulose &lt;suzuki.poulose@arm.com&gt;
Reviewed-by: James Morse &lt;james.morse@arm.com&gt;
Signed-off-by: Amit Daniel Kachhap &lt;amit.kachhap@arm.com&gt;
Link: https://lore.kernel.org/r/20221103082232.19189-1-amit.kachhap@arm.com
Signed-off-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
</content>
</entry>
<entry>
<title>arm64: Add HWCAP advertising FEAT_WFXT</title>
<updated>2022-04-20T12:24:44+00:00</updated>
<author>
<name>Marc Zyngier</name>
<email>maz@kernel.org</email>
</author>
<published>2022-04-20T12:21:12+00:00</published>
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<id>urn:sha1:69bb02ebc38ace438c9cd7c5315cfe43862b51fe</id>
<content type='text'>
In order to allow userspace to enjoy WFET, add a new HWCAP that
advertises it when available.

Signed-off-by: Marc Zyngier &lt;maz@kernel.org&gt;
Acked-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
Link: https://lore.kernel.org/r/20220419182755.601427-9-maz@kernel.org
</content>
</entry>
<entry>
<title>arm64: cpufeature: add HWCAP for FEAT_RPRES</title>
<updated>2021-12-13T18:53:00+00:00</updated>
<author>
<name>Joey Gouly</name>
<email>joey.gouly@arm.com</email>
</author>
<published>2021-12-10T16:54:32+00:00</published>
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<id>urn:sha1:1175011a7d0030d49dc9c10bde36f08f26d0a8ee</id>
<content type='text'>
Add a new HWCAP to detect the Increased precision of Reciprocal Estimate
and Reciprocal Square Root Estimate feature (FEAT_RPRES), introduced in Armv8.7.

Also expose this to userspace in the ID_AA64ISAR2_EL1 feature register.

Signed-off-by: Joey Gouly &lt;joey.gouly@arm.com&gt;
Cc: Will Deacon &lt;will@kernel.org&gt;
Cc: Jonathan Corbet &lt;corbet@lwn.net&gt;
Acked-by: Marc Zyngier &lt;maz@kernel.org&gt;
Link: https://lore.kernel.org/r/20211210165432.8106-4-joey.gouly@arm.com
Signed-off-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
</content>
</entry>
<entry>
<title>arm64: cpufeature: add HWCAP for FEAT_AFP</title>
<updated>2021-12-13T18:52:59+00:00</updated>
<author>
<name>Joey Gouly</name>
<email>joey.gouly@arm.com</email>
</author>
<published>2021-12-10T16:54:30+00:00</published>
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<id>urn:sha1:5c13f042e73200b50573ace63e1a6b94e2917616</id>
<content type='text'>
Add a new HWCAP to detect the Alternate Floating-point Behaviour
feature (FEAT_AFP), introduced in Armv8.7.

Also expose this to userspace in the ID_AA64MMFR1_EL1 feature register.

Signed-off-by: Joey Gouly &lt;joey.gouly@arm.com&gt;
Cc: Will Deacon &lt;will@kernel.org&gt;
Acked-by: Marc Zyngier &lt;maz@kernel.org&gt;
Link: https://lore.kernel.org/r/20211210165432.8106-2-joey.gouly@arm.com
Signed-off-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
</content>
</entry>
<entry>
<title>arm64: Add HWCAP for self-synchronising virtual counter</title>
<updated>2021-10-19T09:56:20+00:00</updated>
<author>
<name>Marc Zyngier</name>
<email>maz@kernel.org</email>
</author>
<published>2021-10-17T12:42:25+00:00</published>
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<id>urn:sha1:fee29f008aa3f2aff01117f28b57b1145d92cb9b</id>
<content type='text'>
Since userspace can make use of the CNTVSS_EL0 instruction, expose
it via a HWCAP.

Suggested-by: Will Deacon &lt;will@kernel.org&gt;
Acked-by: Will Deacon &lt;will@kernel.org&gt;
Signed-off-by: Marc Zyngier &lt;maz@kernel.org&gt;
Link: https://lore.kernel.org/r/20211017124225.3018098-18-maz@kernel.org
Signed-off-by: Will Deacon &lt;will@kernel.org&gt;
</content>
</entry>
<entry>
<title>arm64: mte: Add Memory Tagging Extension documentation</title>
<updated>2020-09-04T11:46:07+00:00</updated>
<author>
<name>Vincenzo Frascino</name>
<email>vincenzo.frascino@arm.com</email>
</author>
<published>2019-09-06T09:52:39+00:00</published>
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<id>urn:sha1:df9d7a22dd21c926e8175ccc6e176cb45fc7cb09</id>
<content type='text'>
Memory Tagging Extension (part of the ARMv8.5 Extensions) provides
a mechanism to detect the sources of memory related errors which
may be vulnerable to exploitation, including bounds violations,
use-after-free, use-after-return, use-out-of-scope and use before
initialization errors.

Add Memory Tagging Extension documentation for the arm64 linux
kernel support.

Signed-off-by: Vincenzo Frascino &lt;vincenzo.frascino@arm.com&gt;
Co-developed-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
Signed-off-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
Acked-by: Szabolcs Nagy &lt;szabolcs.nagy@arm.com&gt;
Cc: Will Deacon &lt;will@kernel.org&gt;
</content>
</entry>
<entry>
<title>arm64: Documentation: Fix broken table in generated HTML</title>
<updated>2020-07-08T21:20:41+00:00</updated>
<author>
<name>Suzuki K Poulose</name>
<email>suzuki.poulose@arm.com</email>
</author>
<published>2020-07-07T14:31:52+00:00</published>
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<id>urn:sha1:581fce373581772470af8fb4fe13505dc66281e6</id>
<content type='text'>
cpu-feature-registers.rst is missing a new line before a couple
of tables listing the visible fields, causing broken tables in
the HTML documentation generated by "make htmldocs". Fix this
by adding the missing new line.

Reported-by: Peter Maydell &lt;peter.maydell@linaro.org&gt;
Signed-off-by: Suzuki K Poulose &lt;suzuki.poulose@arm.com&gt;
Cc: Mark Rutland &lt;mark.rutland@arm.com&gt;
Cc: Will Deacon &lt;will.deacon@arm.com&gt;
Cc: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
Link: https://lore.kernel.org/r/20200707143152.154541-1-suzuki.poulose@arm.com
Signed-off-by: Will Deacon &lt;will@kernel.org&gt;
</content>
</entry>
<entry>
<title>arm64: Basic Branch Target Identification support</title>
<updated>2020-03-16T17:19:48+00:00</updated>
<author>
<name>Dave Martin</name>
<email>Dave.Martin@arm.com</email>
</author>
<published>2020-03-16T16:50:45+00:00</published>
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<id>urn:sha1:8ef8f360cf30be12382f89ff48a57fbbd9b31c14</id>
<content type='text'>
This patch adds the bare minimum required to expose the ARMv8.5
Branch Target Identification feature to userspace.

By itself, this does _not_ automatically enable BTI for any initial
executable pages mapped by execve().  This will come later, but for
now it should be possible to enable BTI manually on those pages by
using mprotect() from within the target process.

Other arches already using the generic mman.h are already using
0x10 for arch-specific prot flags, so we use that for PROT_BTI
here.

For consistency, signal handler entry points in BTI guarded pages
are required to be annotated as such, just like any other function.
This blocks a relatively minor attack vector, but comforming
userspace will have the annotations anyway, so we may as well
enforce them.

Signed-off-by: Mark Brown &lt;broonie@kernel.org&gt;
Signed-off-by: Dave Martin &lt;Dave.Martin@arm.com&gt;
Reviewed-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
Signed-off-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 'for-next/rng' into for-next/core</title>
<updated>2020-01-22T11:38:53+00:00</updated>
<author>
<name>Will Deacon</name>
<email>will@kernel.org</email>
</author>
<published>2020-01-22T11:38:53+00:00</published>
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<id>urn:sha1:bc206065944e2d6bd917e719dc897ffff8dbbca8</id>
<content type='text'>
* for-next/rng: (2 commits)
  arm64: Use v8.5-RNG entropy for KASLR seed
  ...
</content>
</entry>
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