Linux kernel mainline source http://mirrors.hust.edu.cn/git/linux.git/atom?h=master 2026-08-21T21:40:46+00:00 2026-08-21T21:40:46+00:00 Bjorn Helgaas bhelgaas@google.com 2026-08-21T21:40:46+00:00 urn:sha1:b130a2caf5d3f65c14e9524c65bcf0d64be298d9 - Distinguish Tegra264 C0 PCIe controller for internal GPU from C1-C5 controllers so the unit address matches the first 'reg' entry (Thierry Reding) - Add Tegra264 Root Port stanzas to prepare for generic WAKE# handling (Thierry Reding) - Add NVIDIA Tegra264 driver (Thierry Reding) * pci/controller/tegra264: PCI: tegra264: Add Tegra264 support dt-bindings: PCI: tegra264: Switch to PCIe Root Port bindings dt-bindings: PCI: tegra264: Strictly distinguish C0 from C1-C5 2026-08-19T17:13:16+00:00 Thierry Reding treding@nvidia.com 2026-08-14T15:38:57+00:00 urn:sha1:01c3c27a0ef6a7f63559dba33c62377c21fc3ee9 Add a driver for the PCIe controller found on NVIDIA Tegra264 SoCs. The driver is very basic, with its main purpose being to set up the address translation registers and then registering a standard PCIe Host Bridge making use of ECAM. Co-developed-by: Manikanta Maddireddy <mmaddireddy@nvidia.com> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> [mani: tweaked MAINTAINERS entry to support this new driver and binding] Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://patch.msgid.link/20260814-tegra264-pcie-v10-3-05d08c592b05@nvidia.com 2026-07-15T13:49:04+00:00 Caleb James DeLisle cjd@cjdns.fr 2026-07-02T15:07:04+00:00 urn:sha1:2077ccb9baa2cbbbccf5f0d8c2196dd9d5e43399 Add support for the PCIe controller present in the EcoNet EN7528 (and EN751221) SoCs. The PCIe controllers present in these SoCs support 2.5 GT/s and 5 GT/s data rates, but 5 GT/s require re-training after link up. Co-developed-by: Ahmed Naseef <naseefkm@gmail.com> Signed-off-by: Ahmed Naseef <naseefkm@gmail.com> Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr> [mani: commit log] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://patch.msgid.link/20260702150704.265282-1-cjd@cjdns.fr 2026-04-24T16:54:45+00:00 Linus Torvalds torvalds@linux-foundation.org 2026-04-24T16:54:45+00:00 urn:sha1:ff57d59200baadfdb41f94a49fed7d161a9a8124 Pull LoongArch updates from Huacai Chen: - Adjust build infrastructure for 32BIT/64BIT - Add HIGHMEM (PKMAP and FIX_KMAP) support - Show and handle CPU vulnerabilites correctly - Batch the icache maintenance for jump_label - Add more atomic instructions support for BPF JIT - Add more features (e.g. fsession) support for BPF trampoline - Some bug fixes and other small changes * tag 'loongarch-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson: (21 commits) selftests/bpf: Enable CAN_USE_LOAD_ACQ_STORE_REL for LoongArch LoongArch: BPF: Add fsession support for trampolines LoongArch: BPF: Introduce emit_store_stack_imm64() helper LoongArch: BPF: Support up to 12 function arguments for trampoline LoongArch: BPF: Support small struct arguments for trampoline LoongArch: BPF: Open code and remove invoke_bpf_mod_ret() LoongArch: BPF: Support load-acquire and store-release instructions LoongArch: BPF: Support 8 and 16 bit read-modify-write instructions LoongArch: BPF: Add the default case in emit_atomic() and rename it LoongArch: Define instruction formats for AM{SWAP/ADD}.{B/H} and DBAR LoongArch: Batch the icache maintenance for jump_label LoongArch: Add flush_icache_all()/local_flush_icache_all() LoongArch: Add spectre boundry for syscall dispatch table LoongArch: Show CPU vulnerabilites correctly LoongArch: Make arch_irq_work_has_interrupt() true only if IPI HW exist LoongArch: Use get_random_canary() for stack canary init LoongArch: Improve the logging of disabling KASLR LoongArch: Align FPU register state to 32 bytes LoongArch: Handle CONFIG_32BIT in syscall_get_arch() LoongArch: Add HIGHMEM (PKMAP and FIX_KMAP) support ... 2026-04-22T07:44:26+00:00 Huacai Chen chenhuacai@loongson.cn 2026-04-22T07:44:26+00:00 urn:sha1:3d9aba6618d115750729bba2d1f8af180bd7d3bd Adjust build infrastructure (Kconfig, Makefile and ld scripts) to let us enable both 32BIT/64BIT kernel build. Reviewed-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn> 2026-03-25T18:47:51+00:00 Chen-Yu Tsai wenst@chromium.org 2026-03-24T05:19:59+00:00 urn:sha1:1a152e21940a18caf7c9d0d753a46d2ffa3f5010 With the new PCI pwrctrl API and PCI slot binding and power drivers, we now have a way to describe and power up WiFi/BT adapters connected through a PCIe or M.2 slot, or populated onto the mainboard itself. The latter case has the adapter layout or design copied verbatim, replacing the slot with direct connections. Integrate the PCI pwrctrl API into the PCIe driver, so that power is properly enabled before PCIe link training is done, allowing the card to successfully be detected. Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://patch.msgid.link/20260324052002.4072430-8-wenst@chromium.org 2026-02-06T23:09:52+00:00 Bjorn Helgaas bhelgaas@google.com 2026-02-06T23:09:52+00:00 urn:sha1:522a46affdceda863df9bf652119f463f480479d - Add rcar-host OF Kconfig dependency to avoid objtool no-cfi warning (Nathan Chancellor) * pci/controller/misc: PCI: rcar-host: Add OF Kconfig dependency to avoid objtool no-cfi warning 2026-02-06T23:09:50+00:00 Bjorn Helgaas bhelgaas@google.com 2026-02-06T23:09:50+00:00 urn:sha1:5b4e5be1ccb41b1ba3a252a4736f298ef7bd5dec - Export irq_domain_free_irqs() to allow PCI/MSI drivers that tear down MSI domains to be built as modules (Aaron Kling) - Export tegra_cpuidle_pcie_irqs_in_use(), which disables Tegra CC6 while PCI IRQs are in use, so pci-tegra can be built as a module (Aaron Kling) - Allow pci-tegra to be built as a module (Aaron Kling) * pci/controller/tegra: PCI: tegra: Allow building as a module cpuidle: tegra: Export tegra_cpuidle_pcie_irqs_in_use() irqdomain: Export irq_domain_free_irqs() 2025-12-26T16:57:17+00:00 Aaron Kling webgeek1234@gmail.com 2025-07-31T21:59:26+00:00 urn:sha1:aac5ba6acc79b37b01dfc9dd23eb457c89cf06f6 Change the module macro back to builtin, which does not define an exit function. This will prevent the module from being unloaded. There are concerns with modules not cleaning up IRQs on unload, thus unload must be specifically disallowed. Drop the remove callback as it is unused. Signed-off-by: Aaron Kling <webgeek1234@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://patch.msgid.link/20250731-pci-tegra-module-v7-3-cad4b088b8fb@gmail.com 2025-12-23T15:55:20+00:00 Jacky Chou jacky_chou@aspeedtech.com 2025-12-16T01:50:05+00:00 urn:sha1:9aa0cb68fcc16280c8c8bdd22dc770af8dd7349f Introduce PCIe Root Complex driver for ASPEED SoCs. Support RC initialization, reset, clock, IRQ domain, and MSI domain setup. Implement platform-specific setup and register configuration for ASPEED. And provide PCI config space read/write and INTx/MSI interrupt handling. Signed-off-by: Jacky Chou <jacky_chou@aspeedtech.com> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://patch.msgid.link/20251216-upstream_pcie_rc-v7-6-4aeb0f53c4ce@aspeedtech.com