<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux.git/drivers/gpu/drm/amd/pm, branch master</title>
<subtitle>Linux kernel mainline source</subtitle>
<id>http://mirrors.hust.edu.cn/git/linux.git/atom?h=master</id>
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<updated>2026-08-20T00:58:44+00:00</updated>
<entry>
<title>BackMerge tag 'v7.2' into drm-next</title>
<updated>2026-08-20T00:58:44+00:00</updated>
<author>
<name>Dave Airlie</name>
<email>airlied@redhat.com</email>
</author>
<published>2026-08-20T00:58:44+00:00</published>
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<id>urn:sha1:c44e278ce02efd0c4be79a8eda1ea6885c1ce5ec</id>
<content type='text'>
Linux 7.2

There was a lot of conflicts this round between fixes and next,
and I'd like to get the merge resolutions that we have in drm-tip.

Signed-off-by: Dave Airlie &lt;airlied@redhat.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/pm: silence uninitialized variable warnings</title>
<updated>2026-08-12T13:44:35+00:00</updated>
<author>
<name>Dan Carpenter</name>
<email>error27@gmail.com</email>
</author>
<published>2026-08-08T19:41:28+00:00</published>
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<id>urn:sha1:b4cb43789b6ac0f25fc0d9b21c5e7a6225cf6a31</id>
<content type='text'>
Smatch complains that:

    drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu15/smu_v15_0_8_ppt.c:1964
    smu_v15_0_8_set_performance_level() error: uninitialized symbol 'ret'.

In this line there is an "if (ret)" condition where "ret" is either
zero or uninitialized.  Initialize "ret" at the start of the function to
avoid a potential uninitialized variable bug.  But also delete the
condition since it is never true.

Fixes: 422b399b09c7 ("drm/amd/pm: Add od_edit_dpm_table support")
Reviewed-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Signed-off-by: Dan Carpenter &lt;error27@gmail.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Enable GFXOFF functionality for SMU IP v15.0.5</title>
<updated>2026-08-12T13:36:28+00:00</updated>
<author>
<name>Shubhankar Milind Sardeshpande</name>
<email>Shubhankar.MilindSardeshpande@amd.com</email>
</author>
<published>2026-08-05T11:43:00+00:00</published>
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<id>urn:sha1:92b0cbfbba4a162831128c4b339a45b2ab5fc351</id>
<content type='text'>
Add clockgating and powergating flags for GC 11.5.6
and allow/disallow GFXOFF for SMU 15.0.5

Signed-off-by: Shubhankar Milind Sardeshpande &lt;Shubhankar.MilindSardeshpande@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Pratik Vishwakarma &lt;Pratik.Vishwakarma@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/pm: Keep sub-degree precision in Q10 temperatures</title>
<updated>2026-08-12T13:36:24+00:00</updated>
<author>
<name>Lijo Lazar</name>
<email>lijo.lazar@amd.com</email>
</author>
<published>2026-08-04T08:58:12+00:00</published>
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<id>urn:sha1:1f33a9688f2018aba8c9b7476f50999c10c6a921</id>
<content type='text'>
The Q10 temperatures were rounded to whole degrees before being scaled
to millidegrees, losing sub-degree precision. Convert them while
preserving the fractional part.

Also, use the standard MILLIDEGREE_PER_DEGREE to represent
SMU_TEMPERATURE_UNITS_PER_CENTIGRADES.

Signed-off-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Reviewed-by: Asad Kamal &lt;asad.kamal@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/pm: Keep sub-watt precision in Q10 socket power</title>
<updated>2026-08-12T13:36:15+00:00</updated>
<author>
<name>Lijo Lazar</name>
<email>lijo.lazar@amd.com</email>
</author>
<published>2026-08-04T08:41:47+00:00</published>
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<id>urn:sha1:a01ff85d6f09d83786233c6defe4f5bdfc5ff695</id>
<content type='text'>
The Q10 socket power was rounded to whole watts before scaling to
milliwatts, so the reported value lost its sub-watt precision. Add
SMUQ10_TO_MILLIWATT to convert while keeping the fractional bits.

Signed-off-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Reviewed-by: Asad Kamal &lt;asad.kamal@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/pm: Simplify SoC power printing in debugfs</title>
<updated>2026-08-12T13:36:09+00:00</updated>
<author>
<name>Lijo Lazar</name>
<email>lijo.lazar@amd.com</email>
</author>
<published>2026-08-04T07:41:51+00:00</published>
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<id>urn:sha1:f5998f4d71b233c88f0661ace2f36a6dcb9d689a</id>
<content type='text'>
Convert SoC power directly from milliwatts using MILLIWATT_PER_WATT and
remove redundant variables.

Signed-off-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Reviewed-by: Asad Kamal &lt;asad.kamal@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/pm: smu_v14_0_0: use find_clk_level() for DPM level marking</title>
<updated>2026-08-06T13:27:17+00:00</updated>
<author>
<name>Priya Hosur</name>
<email>Priya.Hosur@amd.com</email>
</author>
<published>2026-06-15T05:03:12+00:00</published>
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<id>urn:sha1:39dfe8a7d7092c23e480f35e2cb2760d3e93f7a6</id>
<content type='text'>
Replace the simple exact-match loop in emit_clk_levels with a call
to smu_v14_0_0_find_clk_level() introduced in patch 1.  The helper
already handles both exact and closest-match semantics.

Build a stack-local frequency table from the DPM levels (using
reverse index for SMU_MCLK since MemPstateTable stores levels
high-to-low), then call the helper once to find the active level.

The SMU reports time-filtered average frequencies that often do not
match any DPM table entry exactly.  Without closest-match fallback,
MCLK, FCLK and other clocks show DPM levels but never display the
* marker, breaking userspace tools that rely on it to identify the
active frequency.

Signed-off-by: Priya Hosur &lt;Priya.Hosur@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/pm: smu_v14_0_0: add SMU_DCEFCLK support in DPM frequency queries</title>
<updated>2026-08-06T13:27:12+00:00</updated>
<author>
<name>Priya Hosur</name>
<email>Priya.Hosur@amd.com</email>
</author>
<published>2026-06-04T13:04:18+00:00</published>
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<id>urn:sha1:ae60a2b05f813d434591c2d897222ba9cdff173f</id>
<content type='text'>
Add SMU_DCEFCLK case to smu_v14_0_1_get_dpm_freq_by_index and
smu_v14_0_0_get_dpm_freq_by_index using DcfClocks[] with
NumDcfClkLevelsEnabled bounds check. Add matching case in both
get_dpm_level_count functions.

Add SMU_DCEFCLK case in emit_clk_levels to list DCEF DPM levels.
No * marker is emitted since SmuMetrics_t has no DcfclkFrequency
field (same firmware limitation as Phoenix).

Without this, pp_dpm_dcefclk reports N/A on Strix Halo.

Signed-off-by: Priya Hosur &lt;Priya.Hosur@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/pm: add IP_VERSION(11,5,1) to vclk/dclk DPM sysfs whitelists</title>
<updated>2026-08-06T13:27:07+00:00</updated>
<author>
<name>Priya Hosur</name>
<email>Priya.Hosur@amd.com</email>
</author>
<published>2026-06-04T13:03:14+00:00</published>
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<id>urn:sha1:19d408ea197a66d3a20818e759ca216eb9020760</id>
<content type='text'>
Add IP_VERSION(11,5,1) to pp_dpm_vclk and pp_dpm_dclk visibility
whitelists so these sysfs entries are exposed on Strix Halo (GC
11.5.1). Add IP_VERSION(11,5,1) to pp_dpm_vclk1 and pp_dpm_dclk1
whitelists with the existing num_vcn_inst &gt;= 2 guard since Strix
Halo has two VCN instances.

Without this, amd-smi reports N/A for VCLK0, VCLK1, DCLK0 and
DCLK1 clocks.

Signed-off-by: Priya Hosur &lt;Priya.Hosur@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/pm: smu_v14_0_0: fix DCLK metric reporting via VCLK level index</title>
<updated>2026-08-06T13:26:56+00:00</updated>
<author>
<name>Priya Hosur</name>
<email>Priya.Hosur@amd.com</email>
</author>
<published>2026-06-15T04:59:15+00:00</published>
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<id>urn:sha1:abbc038bcbdbef1a4daa0c14d285e00e024a59e8</id>
<content type='text'>
SmuMetrics_t has no DclkFrequency field but DCLK and VCLK have
separate DPM clock tables with different frequencies at each level.

Introduce smu_v14_0_0_find_clk_level(), a shared helper that
finds the closest DPM level for a given target frequency in a
frequency array.

For METRICS_AVERAGE_DCLK, use the helper to find the DPM level
whose VCLK frequency matches the reported VclkFrequency and
return the DCLK frequency at that same level index, since both
clocks share the same level count (VcnClkLevelsEnabled /
Vcn0ClkLevelsEnabled).

The original code returned 0 for METRICS_AVERAGE_DCLK, which broke
the active-level marker in pp_dpm_dclk entirely.

Signed-off-by: Priya Hosur &lt;Priya.Hosur@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
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