linux-next.git/include/linux/soc/qcom/ubwc.h, branch master

soc: qcom: ubwc: Add configuration for Hawi

2026-08-31T23:10:55+00:00

Add UBWC configuration data for the Hawi platform, which uses UBWC 7.0 and enables the required flags and highest bank bit settings. This allows drivers to query the correct UBWC capabilities on Hawi. Also add UBWC 7.0 support to the version tag helper so that qcom_ubwc_version_tag() returns the correct tag for UBWC 7.0. Signed-off-by: Wangao Wang Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260812-ubwc_for_hawi_maili-v1-1-c29edecb3bd8@oss.qualcomm.com Signed-off-by: Bjorn Andersson

soc: qcom: ubwc: Fix missing include

2026-08-18T09:17:52+00:00

When CONFIG_QCOM_UBWC_CONFIG=n, compiler needs to know the definition of ERR_PTR otherwise there will be a compilation error: In file included from drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp_v13.c:7: ./include/linux/soc/qcom/ubwc.h: In function ‘qcom_ubwc_config_get_data’: ./include/linux/soc/qcom/ubwc.h:45:16: error: implicit declaration of function ‘ERR_PTR’ [-Wimplicit-function-declaration] Fix this by including Fixes: 1924272b9ce1 ("soc: qcom: Add UBWC config provider") Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Daniel Baluta Tested-by: Nathan Chancellor # build Signed-off-by: Arnd Bergmann

soc: qcom: ubwc: sort out the rest of the UBWC swizzle settings

2026-07-05T19:37:23+00:00

Sort out the remaining UBWC swizzle values, using flags to control whether level 2 and level 3 swizzling are enabled or not. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260520-ubwc-rework-v5-27-72f2749bc807@oss.qualcomm.com Signed-off-by: Bjorn Andersson

soc: qcom: ubwc: use fixed values for UBWC swizzle for UBWC < 4.0

2026-07-05T19:37:23+00:00

UBWC devices before 4.0 use standard UBWC swizzle levels. As all the drivers now use the qcom_ubwc_swizzle() helper, move those values to the helper, leaving UBWC 4.0+ intact for now. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260520-ubwc-rework-v5-26-72f2749bc807@oss.qualcomm.com Signed-off-by: Bjorn Andersson

soc: qcom: ubwc: drop macrotile_mode from the database

2026-07-05T19:37:23+00:00

All the users have been migrated to using qcom_ubwc_macrotile_mode() instead of reading the raw value from the config structure. Drop the field from struct qcom_ubwc_cfg_data and replace it with the calculated value. Split single UBWC_3_0 into UBWC_3_0 (no macrotile mode) and UBWC_3_1 (with macrotile mode). Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260520-ubwc-rework-v5-25-72f2749bc807@oss.qualcomm.com Signed-off-by: Bjorn Andersson

soc: qcom: ubwc: drop ubwc_bank_spread

2026-07-05T19:37:23+00:00

According to the documentation, UBWC bank spreading should be enabled for all targets. It's just not all targets have separate bit to control it. Drop the bit from the database and make the helper always return true. If we need to change it later, the helper can be adjusted according to the programming guides. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260520-ubwc-rework-v5-24-72f2749bc807@oss.qualcomm.com Signed-off-by: Bjorn Andersson

soc: qcom: ubwc: drop ubwc_dec_version

2026-07-05T19:37:23+00:00

The ubwc_dec_version field has been inherited from the MDSS driver and it is equal to the version of the UBWC decoder in the display block only. Other IP Cores can have different UBWC decoders and so the version would vary between blocks. As the value is no longer used as is not relevant to other UBWC database consumers, drop it from the UBWC database. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260520-ubwc-rework-v5-23-72f2749bc807@oss.qualcomm.com Signed-off-by: Bjorn Andersson

soc: qcom: ubwc: set min_acc length to 64 for all UBWC 1.0 targets

2026-07-05T19:37:22+00:00

According to the documentation, the MAL should be set for all UBWC 1.0 targets, no matter what is the version of the UBWC decoders are present on the device. The helper comes from DPU / GPU world, where there was no separate bit to control MAL before UBWC 2.0. As the helper is now being used by other drivers too, correct the helper to return the correct MAL value (Iris doesn't support UBWC 1.0 devices for now, so there is no changes of the behaviour). Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260520-ubwc-rework-v5-22-72f2749bc807@oss.qualcomm.com Signed-off-by: Bjorn Andersson

soc: qcom: ubwc: add helper controlling AMSBC enablement

2026-05-20T02:29:19+00:00

Adreno and MDSS drivers need to know whether to enable AMSBC. Add separate helper, describing that feature. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260507-ubwc-rework-v4-4-c19593d20c1d@oss.qualcomm.com Signed-off-by: Bjorn Andersson

soc: qcom: ubwc: define helper for MDSS and Adreno drivers

2026-05-20T02:29:19+00:00

Define special helper returning version setting for MDSS and A8xx drivers. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260507-ubwc-rework-v4-3-c19593d20c1d@oss.qualcomm.com Signed-off-by: Bjorn Andersson