linux-next.git/drivers/memory/tegra/mc.c, branch master

memory: tegra: Guard against NULL mc_regs in IRQ handler

2026-07-08T11:14:48+00:00

The per-error decode in tegra30_mc_handle_irq() dereferences mc->soc->regs unconditionally. This 'regs' structure is optional and is only used for decoding and logging MC error interrupts. The rest of the MC functionality does not depend on it. When adding support for the Tegra238 SoC, the 'regs' structure was initially omitted because it is only used for error logging. We found that this resulted in a NULL pointer dereference in IRQ context, causing a crash when an MC error interrupt fired. Although existing upstream devices will not hit this condition because 'regs' is present, guard against it to improve the robustness of the driver. Skip the decode and just clear the interrupt when mc_regs is NULL. This bypasses the error interrupt logging while keeping the remaining MC functionality intact. Signed-off-by: Ashish Mhetre Link: https://patch.msgid.link/20260703045653.395498-1-amhetre@nvidia.com Signed-off-by: Krzysztof Kozlowski

memory: tegra: add multi-socket support to the memory interconnect

2026-07-08T11:10:09+00:00

Add support for representing each memory-controller instance (one per NUMA node / socket) as its own interconnect (ICC) provider, with its own MC client nodes, to match the hardware topology on multi-socket Tegra SoCs. Use the NUMA node ID to make client IDs globally unique across per-socket providers, since the ICC framework allocates node IDs from a single global IDR. Per-socket MC and EMC node names are also derived from dev_name() so they match the corresponding debugfs subdirectory. On single-socket platforms (NUMA_NO_NODE) the existing client IDs and node-name strings are preserved. Each socket's MC and EMC therefore get their own debugfs subdirectory under /sys/kernel/debug/{mc,emc}/. The parent directories are created on first probe. Bandwidth requests from MC clients in a socket are routed to that socket's local BPMP. Signed-off-by: Sumit Gupta Tested-by: Jon Hunter Reviewed-by: Jon Hunter Link: https://patch.msgid.link/20260626131423.3986998-1-sumitg@nvidia.com Signed-off-by: Krzysztof Kozlowski

memory: tegra: Add Tegra238 MC support

2026-05-04T17:27:15+00:00

Add Memory Controller driver support for Tegra238 SOC, including: - MC client definitions with Tegra238-specific stream IDs - Reuse of Tegra234 ICC operations for bandwidth management via BPMP-FW - Device tree compatible string "nvidia,tegra238-mc" Export tegra234_mc_icc_ops so it can be shared with the Tegra238 MC driver, as both SoCs use the same ICC aggregation and bandwidth management logic. Signed-off-by: Ashish Mhetre Reviewed-by: Jon Hunter Link: https://patch.msgid.link/20260427073419.567360-3-amhetre@nvidia.com Signed-off-by: Krzysztof Kozlowski

memory: tegra: Restore MC interrupt masks on resume

2026-05-04T17:17:56+00:00

The MC interrupt mask registers lose their state across Tegra low power suspend state (aka. SC7). Without re-applying them on resume, MC interrupts that were enabled at probe remain masked after wake, so any post-resume MC error goes unreported. Factor the existing intmask programming out of tegra_mc_probe() into tegra_mc_setup_intmask() and reuse it from the system resume callback so the mask state is restored on wake. Signed-off-by: Ashish Mhetre Reviewed-by: Jon Hunter Link: https://patch.msgid.link/20260430095202.1167651-4-amhetre@nvidia.com Signed-off-by: Krzysztof Kozlowski

memory: tegra: Wire up system sleep PM ops

2026-05-04T17:17:48+00:00

The tegra-mc platform driver does not register any dev_pm_ops, so the SoC-specific ->resume() is never invoked (e.g. tegra186_mc_resume) on system wake. On Tegra186 and later this means MC client Stream-ID override registers are not reprogrammed, and clients behind the ARM SMMU fault on the first DMA after resume. Register a dev_pm_ops on the tegra-mc driver and route the system resume callback into mc->soc->ops->resume() so the existing SID restore path runs again on wake. No suspend callback is needed as the resume path reprograms all MC state from the static SoC tables, so there is nothing to save. Fixes: fe3b082a6eb8 ("memory: tegra: Add SID override programming for MC clients") Signed-off-by: Ashish Mhetre Reviewed-by: Jon Hunter Link: https://patch.msgid.link/20260430095202.1167651-3-amhetre@nvidia.com Signed-off-by: Krzysztof Kozlowski

memory: tegra: Add MC error logging support for Tegra264

2026-03-07T17:02:48+00:00

In Tegra264, different components from memory subsystems like Memory Controller Fabric (MCF), HUB, HUB Common (HUBC), Side Band Shim (SBS) and channels have different interrupt lines for receiving memory controller error interrupts. Add support for logging memory controller errors reported by these memory subsystems on Tegra264 by: - Renaming tegra_mc_error_names array to tegra20_mc_error_names because it has a different bit index for error names compared to Tegra264. - Defining the intmask registers and mask values supported for Tegra264. - Registering interrupt handlers for interrupts associated with these different MC components which read the interrupt status registers to determine the type of violation that occurred. Signed-off-by: Ketan Patil Reviewed-by: Jon Hunter Tested-by: Jon Hunter Link: https://patch.msgid.link/20260226163115.1152181-7-ketanp@nvidia.com Signed-off-by: Krzysztof Kozlowski

memory: tegra: Prepare for supporting multiple intmask registers

2026-03-07T17:02:41+00:00

Add a new structure for the intmask register e.g. MC_INTMASK_0 and it's mask value. Add an array of these new structures to prepare for supporting multiple intmask registers. This is done in preparation for adding support for Tegra264 which supports multiple intmask registers. Signed-off-by: Ketan Patil Reviewed-by: Jon Hunter Tested-by: Jon Hunter Link: https://patch.msgid.link/20260226163115.1152181-6-ketanp@nvidia.com [krzk: Fix checkpatch warning] Signed-off-by: Krzysztof Kozlowski

memory: tegra: Group SoC specific fields

2026-03-07T17:02:29+00:00

Introduce new SoC specific fields in tegra_mc_soc struct for high address mask and error status type mask because Tegra264 has different values for these than the existing devices. Error status registers e.g. MC_ERR_STATUS_0 has few bits which indicate the type of the error. In order to obtain such type of error from error status register, we use error status type mask. Similarly, these error status registers have bits which indicate the higher address bits of the address responsible for mc error. In order to obtain such higher address, we use high address mask. Make this change to prepare for adding MC interrupt support for Tegra264. Signed-off-by: Ketan Patil Reviewed-by: Jon Hunter Tested-by: Jon Hunter Link: https://patch.msgid.link/20260226163115.1152181-5-ketanp@nvidia.com [krzk: Fix checkpatch warning] Signed-off-by: Krzysztof Kozlowski

memory: tegra: Add support for multiple IRQs

2026-03-07T16:59:37+00:00

Add support to handle multiple MC interrupts lines, as supported by Tegra264. Turn the single IRQ handler callback into a counted array to allow specifying a separate handler for each interrupt. Move IRQ handlers into tegra_mc_soc struct, so as to specify SoC specific values. Signed-off-by: Ketan Patil Reviewed-by: Jon Hunter Tested-by: Jon Hunter Link: https://patch.msgid.link/20260226163115.1152181-4-ketanp@nvidia.com Signed-off-by: Krzysztof Kozlowski

memory: tegra: Group error handling related registers

2026-03-07T16:59:35+00:00

Group MC error related registers into a struct as they could have SoC specific values. Tegra264 has different register offsets than the existing devices and so in order to add support for Tegra264 we need to first make this change. Signed-off-by: Ketan Patil Reviewed-by: Jon Hunter Tested-by: Jon Hunter Link: https://patch.msgid.link/20260226163115.1152181-2-ketanp@nvidia.com Signed-off-by: Krzysztof Kozlowski