linux-next.git/drivers/gpu/nova-core/fb/hal, branch master

gpu: nova-core: return non-WPR heap size as u64 from HALs

2026-08-05T05:20:37+00:00

This is always immediately widened to u64, so just return it as a u64 from the beginning. Signed-off-by: Eliot Courtney Link: https://patch.msgid.link/20260804-blackwell-fixes-v4-3-ac858b6a1935@nvidia.com Signed-off-by: Alexandre Courbot

gpu: nova-core: correct FRTS vidmem offset calculation

2026-08-05T05:20:36+00:00

Currently, the frts vidmem offset is calculated based on the non-wpr heap size and pmu reservation size, but this is not right. The layout actually looks like this: | non-wpr heap | WPR2 .. FRTS | PMU reserved | ... | VGA workspace | It's just by coincidence + generous alignment that the values happened to match. Instead, define a per-architecture reserved size at the end of the framebuffer and use this plus the PMU reserved size to calculate the frts vidmem offset. Fixes: d317e4585fa3 ("gpu: nova-core: Hopper/Blackwell: add FSP Chain of Trust boot") Signed-off-by: Eliot Courtney Link: https://patch.msgid.link/20260804-blackwell-fixes-v4-1-ac858b6a1935@nvidia.com [acourbot: add comment clarifying reason for testing pmu_reserved_size.] [acourbot: make fb_end_reserved_size() return u64.] Signed-off-by: Alexandre Courbot

gpu: nova-core: Move PFB registers definitions

2026-07-30T04:01:13+00:00

Move PFB registers definitions into fb module and update registers visibility. Suggested-by: Alexandre Courbot Suggested-by: Danilo Krummrich Signed-off-by: Antonin Malzieu Ridolfi Link: https://patch.msgid.link/20260727-nova-core-regs-split-v2-2-21b5e6e32ea5@nanonej.com Signed-off-by: Alexandre Courbot

gpu: nova-core: fb: fix Blackwell flush address composition

2026-06-17T07:17:27+00:00

The Blackwell sysmem flush read helper composed the 64-bit address as lo | (hi << 32). Write it as (hi << 32) | lo, the order humans expect to read, matching the bit layout and the new Hopper helper. Signed-off-by: John Hubbard Link: https://patch.msgid.link/20260611011901.84517-4-jhubbard@nvidia.com [acourbot: separate unrelated changes into their own patch.] Signed-off-by: Alexandre Courbot

gpu: nova-core: Hopper: use correct sysmem flush registers

2026-06-17T07:17:21+00:00

Hopper has its own FBHUB sysmem flush page registers, but the Hopper framebuffer HAL delegates to the Ampere NISO path, which encodes the address with an 8-bit right-shift. That programs the wrong value into the wrong registers, so the GPU's sysmembar flush targets the wrong system memory address. Add Hopper's FBHUB flush registers and program them directly from the Hopper HAL. This has not yet been tested on real Hopper hardware (that's true for nova-core in general). Signed-off-by: John Hubbard Link: https://patch.msgid.link/20260611011901.84517-3-jhubbard@nvidia.com Signed-off-by: Alexandre Courbot

gpu: nova-core: Blackwell: use absolute FBHUB0 flush registers

2026-06-17T06:56:17+00:00

The GB20x sysmem flush registers were defined relative to an Fbhub0Base register window, but there is exactly one FBHUB0 base, so expressing them as base-plus-offset only adds indirection. Rename these to FBHUB0 and give them their fixed absolute addresses, dropping the base struct and its RegisterBase impl. No functional changes. Signed-off-by: John Hubbard Link: https://patch.msgid.link/20260611011901.84517-2-jhubbard@nvidia.com Signed-off-by: Alexandre Courbot

gpu: nova-core: move lifetime to `Bar0`

2026-06-03T20:10:51+00:00

Currently Nova code uses `&'a Bar0` a lot. This is `&'a Mmio`, where `Mmio` represents an owned MMIO region; this type only exists as a target for `Deref` so `Bar` and `IoMem` can share code and should be avoided to be named directly. The upcoming I/O projection series would make `Io` trait much simpler to implement, and thus the owned MMIO type would be removed in favour of direct `Io` implementation on `Bar` and `IoMem`. Add lifetime parameter to `Bar0<'a>` and change it to be alias of `&'a pci::Bar<'a, ..>`. This also prepares Nova core so that when I/O projection series land, this could be changed to using a MMIO view type directly which avoids double indirection. Signed-off-by: Gary Guo Acked-by: Alexandre Courbot Reviewed-by: Eliot Courtney Link: https://patch.msgid.link/20260602170416.2268531-1-gary@kernel.org [ Rebase onto latest drm-rust-next (Blackwell enablement). - Danilo ] Signed-off-by: Danilo Krummrich

gpu: nova-core: Blackwell: use correct sysmem flush registers

2026-06-02T13:33:15+00:00

Blackwell GPUs moved the sysmem flush page registers away from the Ampere/Ada location. GB10x routes the flush through a pair of HSHUB0 register sets (primary and egress) that must both be programmed to the same address. GB20x routes it through FBHUB0. Define these registers relative to their HSHUB0 and FBHUB0 bases, as Open RM does, and implement the flush paths in the GB10x and GB20x framebuffer HALs. Signed-off-by: John Hubbard Reviewed-by: Eliot Courtney Link: https://patch.msgid.link/20260602032111.224790-7-jhubbard@nvidia.com Signed-off-by: Alexandre Courbot

gpu: nova-core: Hopper/Blackwell: larger non-WPR heap

2026-06-02T13:33:15+00:00

Hopper and Blackwell need a larger non-WPR heap than the 1 MiB that earlier architectures use. Hopper and Blackwell GB10x need 2 MiB, while Blackwell GB20x needs 2 MiB + 128 KiB. These sizes diverge by family, so give Hopper and each Blackwell family its own framebuffer HAL and select the non-WPR heap size per chipset family. Signed-off-by: John Hubbard Reviewed-by: Eliot Courtney Link: https://patch.msgid.link/20260602032111.224790-5-jhubbard@nvidia.com Signed-off-by: Alexandre Courbot

gpu: nova-core: Blackwell: compute PMU-reserved framebuffer size

2026-06-02T13:33:15+00:00

GSP boot needs to know how much framebuffer memory is reserved for the PMU. Compute it per architecture: Blackwell dGPUs reserve a non-zero amount, earlier architectures leave it at zero, matching Open RM behavior. Signed-off-by: John Hubbard Reviewed-by: Eliot Courtney Link: https://patch.msgid.link/20260602032111.224790-4-jhubbard@nvidia.com Co-developed-by: Alexandre Courbot Signed-off-by: Alexandre Courbot