linux-next.git/drivers/gpu/drm/amd/include/mes_v11_api_def.h, branch masterLinux kernel latest sourcehttp://mirrors.hust.edu.cn/git/linux-next.git/atom?h=master2026-07-01T15:54:18+00:00drm/amdgpu/mes11: set doorbell offset for suspending userq2026-07-01T15:54:18+00:00Prike LiangPrike.Liang@amd.com2026-06-25T02:31:00+00:00urn:sha1:30af09db33696f7e0de5c0c505cbb0cb92b6e25b
Updating the union MESAPI__SUSPEND and union MESAPI__RESUME to
add the doorbell offset for suspending userq.
Signed-off-by: Prike Liang <Prike.Liang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/amdgpu/include : update mes api header v11/v122026-06-17T19:51:34+00:00Shaoyun Liushaoyun.liu@amd.com2026-04-20T14:45:50+00:00urn:sha1:a5b9f68d384a225f56d1b7453eb92b98d58cbe94
Update the parameter in SET_HW_RESOURCES API 1. Align with the setting
of enable_lr_compute_wa 2. Add enable_compute_pipe_reset to enable
pipe reset when compute queue reset failes
v2: add driver flags to track when we enable it
Signed-off-by: Shaoyun Liu <shaoyun.liu@amd.com>
Reviewed-by: Jesse Zhang <jesse.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: update remove after reset flag for MES remove queue2025-10-13T18:14:36+00:00Jonathan Kimjonathan.kim@amd.com2025-06-18T14:45:55+00:00urn:sha1:72ea12f6be3bb57c2118189f7a7cfeb1f7c2748c
Remove queue after reset flag is required to remove a queue that has
been successfully reset to clean up the MES' internal state.
Signed-off-by: Jonathan Kim <jonathan.kim@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Enable MES lr_compute_wa by default2025-09-23T14:22:38+00:00Mario Limonciellomario.limonciello@amd.com2025-09-19T00:48:00+00:00urn:sha1:1fb710793ce2619223adffaf981b1ff13cd48f17
The MES set resources packet has an optional bit 'lr_compute_wa'
which can be used for preventing MES hangs on long compute jobs.
Set this bit by default.
Co-developed-by: Yifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/include : MES v11 and v12 API header update2025-02-13T02:04:06+00:00Shaoyun Liushaoyun.liu@amd.com2025-02-05T18:16:45+00:00urn:sha1:1c687c0da9efb7c627793483a8927554764e7a55
MES requires driver set cleaner_shader_fence_mc_addr
for cleaner shader support.
Signed-off-by: Shaoyun Liu <shaoyun.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd : Update MES API header file for v11 & v122024-11-11T17:22:58+00:00Shaoyun Liushaoyun.liu@amd.com2024-10-18T19:56:25+00:00urn:sha1:ce4971388c79d36b3f50f607c3278dbfae6c789b
New features require the new fields defines
Signed-off-by: Shaoyun Liu <shaoyun.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: increase mes log buffer size for gfx122024-07-27T22:10:12+00:00Michael Chenmichael.chen@amd.com2024-07-23T21:45:23+00:00urn:sha1:9038e25c80558d48ce33d6d8c168666164dc72e9
MES firmware requires larger log buffer for gfx12. Allocate
proper buffer respectively for gfx11 and gfx12.
Signed-off-by: Michael Chen <michael.chen@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit 739d0f3e1f36738d4cd84166784a8f7a58d69612)
drm/amdgpu/mes11: update ADD_QUEUE interface2024-04-26T21:22:45+00:00Jack XiaoJack.Xiao@amd.com2024-04-24T08:41:04+00:00urn:sha1:4b515127e8e09d5d1a9ab119320de36ca6eb52d2
Update ADD_QUEUE interface for mes11 to support
mes mapping legacy queue.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/amdgpu: support MES command SET_HW_RESOURCE1 in sriov2024-04-10T02:08:53+00:00chongli2chongli2@amd.com2024-03-26T05:24:21+00:00urn:sha1:f6ac0842364a5721c02e9dd1c956eb51c7431ff3
support MES command SET_HW_RESOURCE1 in sriov
Signed-off-by: chongli2 <chongli2@amd.com>
Reviewed-by: Jingwen Chen <Jingwen.Chen2@amd.com>
Acked-by: Jingwen Chen <Jingwen.Chen2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdkfd: fix mes set shader debugger process management2023-12-13T21:07:43+00:00Jonathan Kimjonathan.kim@amd.com2023-12-05T17:22:07+00:00urn:sha1:bd33bb1409b494558a2935f7bbc7842def957fcd
MES provides the driver a call to explicitly flush stale process memory
within the MES to avoid a race condition that results in a fatal
memory violation.
When SET_SHADER_DEBUGGER is called, the driver passes a memory address
that represents a process context address MES uses to keep track of
future per-process calls.
Normally, MES will purge its process context list when the last queue
has been removed. The driver, however, can call SET_SHADER_DEBUGGER
regardless of whether a queue has been added or not.
If SET_SHADER_DEBUGGER has been called with no queues as the last call
prior to process termination, the passed process context address will
still reside within MES.
On a new process call to SET_SHADER_DEBUGGER, the driver may end up
passing an identical process context address value (based on per-process
gpu memory address) to MES but is now pointing to a new allocated buffer
object during KFD process creation. Since the MES is unaware of this,
access of the passed address points to the stale object within MES and
triggers a fatal memory violation.
The solution is for KFD to explicitly flush the process context address
from MES on process termination.
Note that the flush call and the MES debugger calls use the same MES
interface but are separated as KFD calls to avoid conflicting with each
other.
Signed-off-by: Jonathan Kim <jonathan.kim@amd.com>
Tested-by: Alice Wong <shiwei.wong@amd.com>
Reviewed-by: Eric Huang <jinhuieric.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>