linux-next.git/drivers/gpu/drm/amd/amdgpu/soc15_common.h, branch master

drm/amdgpu: retire pcs xgmi v6.4.0 legacy ras support

2026-07-01T15:43:22+00:00

retire pcs xgmi v6.4.0 legacy ras support Reviewed-by: Hawking Zhang Signed-off-by: Ce Sun Signed-off-by: Alex Deucher

drm/amdgpu: Only calculate register offset once in SOC15 RLC

2026-06-17T20:32:08+00:00

We can save some text by only calculating the register offset once in a few of the SOC15 RLC register read/write macros. add/remove: 0/0 grow/shrink: 3/69 up/down: 62/-1259 (-1197) ... Total: Before=9896030, After=9894833, chg -0.01% Signed-off-by: Tvrtko Ursulin Signed-off-by: Alex Deucher

drm/amdgpu: Choose SOC15 RLC register read write functions at init time

2026-06-17T20:32:04+00:00

Currently on every RLC register read the driver checks for three different conditions to decide which of the two register read/write functions to call. As these register operations are macros, which is required for register name expansion to work, the result is a significant explosion of generated (redundant) code which the compiler cannot optimise away. We however know that all of the three conditional are static and can therefore move the decision to driver init time. All that we need to do is define a new vfunc table for the SOC12 RLC read/write functions and just use them directly. Bloat-o-meter agrees the driver size savings are significant: add/remove: 11/35 grow/shrink: 82/1117 up/down: 53024/-450922 (-397898) ... Total: Before=10293928, After=9896030, chg -3.87% Signed-off-by: Tvrtko Ursulin Signed-off-by: Alex Deucher

drm/amdgpu: Use get_smn_base in aqua_vanjaram

2026-03-02T21:46:48+00:00

Use get_smn_base interface to get IP die instance's base offset in aqua_vanjaram. encode_ext_smn_addressing is not used. Signed-off-by: Lijo Lazar Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher

drm/amdgpu: Change WREG32_RLC to WREG32_SOC15_RLC where inst != 0 (v2)

2023-11-09T22:03:16+00:00

W/RREG32_RLC is hardedcoded to use instance 0. W/RREG32_SOC15_RLC should be used instead when inst != 0. v2: rebase Signed-off-by: Victor Lu Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher

drm/amdgpu: add pcs xgmi v6.4.0 ras support

2023-11-09T22:02:20+00:00

add pcs xgmi v6.4.0 ras support Signed-off-by: Yang Wang Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher

drm/amdgpu: Add xcc param to SRIOV kiq write and WREG32_SOC15_IP_NO_KIQ (v4)

2023-11-09T22:01:10+00:00

WREG32/RREG32_SOC15_IP_NO_KIQ and amdgpu_virt_kiq_reg_write_reg_wait are not using the correct rlcg interface or mec engine, respectively. Add xcc instance parameter to them. v4: Use GET_INST and squash commit with: "drm/amdgpu: Add xcc_inst param to amdgpu_virt_kiq_reg_write_reg_wait" v3: xcc not needed for MMMHUB v2: rebase Signed-off-by: Victor Lu Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher

drm/amdgpu: Add RLCG interface driver implementation for gfx v9.4.3 (v3)

2023-07-18T15:16:41+00:00

Add RLCG interface support for gfx v9.4.3 and multiple XCCs. Do not enable it yet. v2: Fix amdgpu_rlcg_reg_access_ctrl init, add support for multiple XCCs in amdgpu_mm_wreg_mmio_rlc v3: Use GET_INST() when indexing amdgpu_rlcg_reg_access_ctrl Signed-off-by: Victor Lu Reviewed-by: Zhigang Luo Signed-off-by: Alex Deucher

drm/amdgpu: convert logical instance mask to physical one

2023-06-09T14:37:08+00:00

Convert instance mask for the convenience of RAS TA. Signed-off-by: Tao Zhou Reviewed-by: Hawking Zhang Reviewed-by: Stanley.Yang Signed-off-by: Alex Deucher

drm/amdgpu: fixes a JPEG get write/read pointer bug

2023-06-09T13:56:19+00:00

Need parentheses for the micro parameters. Signed-off-by: Sonny Jiang Reviewed-by: David (Ming Qiang) Wu Signed-off-by: Alex Deucher