linux-next.git/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h, branch master

drm/amdgpu: Delete GMC 8 soft reset

2026-07-01T15:11:44+00:00

We should only reset the memory controller during ASIC reset and only when it's absolutely necessary. Otherwise, resetting the memory controller typically just breaks everything and on dGPUs may also clear the contents of VRAM (it's unclear if it really does, but it's likely). Specifically for GMC 8, the memory controller is reset as part of the ASIC reset and otherwise should be left alone. Reviewed-by: Alex Deucher Signed-off-by: Timur Kristóf Acked-by: Christian König Signed-off-by: Alex Deucher

drm/amdgpu: Use asic specific pte_addr_mask

2026-06-03T17:53:46+00:00

For PTE creation use asic specific physical page base address mask v2: Change variable name from pa_mask to pte_addr_mask Signed-off-by: Harish Kasiviswanathan Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher

drm/amdgpu: Add helper to set gart size

2026-05-05T13:56:51+00:00

Add a helper to make any adjustments to gart size based on other parameters or conditions. Suggested-by: Christian König Signed-off-by: Lijo Lazar Reviewed-by: Christian König Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amdgpu: Move VM PTE MTYPE override to per-PTE granularity

2026-04-28T18:42:22+00:00

Refactor the NUMA-aware MTYPE override for VM page table entries: Move the override_vm_pte_flags call from the centralized amdgpu_vm_pte_update_flags() into the individual CPU and SDMA update backends, enabling per-PTE MTYPE override including for scattered pages (pages_addr path). Move APU, IP version, and direct-mapped eligibility checks from runtime (gmc_v9_0_override_vm_pte_flags) to init time (gmc_v9_0_set_gmc_funcs), to avoid repeated runtime checks on every PTE update. Signed-off-by: Philip Yang Reviewed-by: Christian König Signed-off-by: Alex Deucher

drm/amdgpu: Group filling reserve region details

2026-04-03T17:50:09+00:00

Add a function which groups filling of reserve region information. It may not cover all as info on some regions are still filled outside like those from atomfirmware tables. Signed-off-by: Lijo Lazar Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amdgpu: add support to query vram info from firmware

2026-03-30T19:02:07+00:00

add support to query vram info from firmware v2: change APU vram type, add multi-aid check v3: seperate vram info query function into 3 parts and call them in a helper func when requirements are met. v4: calculate vram_width for v9.x Signed-off-by: Gangliang Xie Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher

drm/amdgpu: use common defines for GMC 12.1 HUB faults

2026-03-11T17:58:07+00:00

Use proper definitions rather than a number. Signed-off-by: Alex Deucher

drm/amdgpu: fix 4-level paging if GMC supports 57-bit VA v2

2026-02-19T17:16:12+00:00

It turned that using 4 level page tables on GMC generations which support 57bit VAs actually doesn't work at all. Background is that the GMC actually can't switch between 4 and 5 levels, but rather just uses a subset of address space when less than 5 levels are selected. Philip already removed the automatically switch to 4levels, now fix it as well should it be enabled by module parameters. v2: fix AMDGPU_GMC_HOLE_MASK as well, fix off by one issue pointed out by Philip Signed-off-by: Christian König Acked-by: Alex Deucher Reviewed-by: Philip Yang Signed-off-by: Alex Deucher

drm/amdgpu: add a helper for processing recoverable GPUVM faults

2025-12-08T19:14:38+00:00

Add a common helper to remove the repeated logic from each gmc module. Suggested-by: Lijo Lazar Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher

drm/amdgpu: Add per-ASIC PTE init flag

2025-12-08T18:56:35+00:00

On GFX12.1, default PTE setup needs an additional bit to be set. Add PTE initialization flags to handle setup default PTE on a per-ASIC basis. While at it, fixup the coding style too. Signed-off-by: Mukul Joshi Reviewed-by: Philip Yang Signed-off-by: Alex Deucher