linux-next.git/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h, branch master

drm/amdkfd: set CP_IQ_WAIT_TIME2.QUE_SLEEP on GFX 12.1

2026-08-25T22:42:29+00:00

The optimized QUE_SLEEP was only programmed on the HWS packet-manager path via a PM4 WRITE_DATA packet, which is skipped when MES is enabled. Add gfx12.1 get_iq_wait_times/build_dequeue_wait_counts_packet_info callbacks and program CP_IQ_WAIT_TIME2 through the MES WRITE_REG op at start_cpsch, per XCC. Signed-off-by: Mukul Joshi Reviewed-by: Harish Kasiviswanathan Signed-off-by: Alex Deucher

drm/amdgpu: Reduce dequeue retry timeout for gfx9 family

2025-03-14T03:10:38+00:00

Dequeue retry timeout controls the interval between checks for unmet conditions. On MI series, reduce this from 0x40 to 0x1 (~ 1 uS). The cost of additional bandwidth consumed by CP when polling memory shouldn't be substantial. Signed-off-by: Harish Kasiviswanathan Reviewed-by: Jonathan Kim Signed-off-by: Alex Deucher

drm/amdkfd: implement per queue sdma reset for gfx 9.4+

2025-03-05T15:47:26+00:00

To reset hung SDMA queues on GFX 9.4+ for the GFX9 family, a soft reset must be issued through SMU. Since soft resets will reset an entire SDMA engine, use a common KGD call to do the reset as the KGD will handle avoiding a reset of in flight GFX and paging queues on that engine. In addition, create a common call for all reset types to simplify the handling of module parameter settings that block gpu resets. Signed-off-by: Jonathan Kim Reviewed-by: Harish Kasiviswanathan Signed-off-by: Alex Deucher

drm/amdkfd: Update logic for CU occupancy calculations

2024-09-25T16:56:00+00:00

Currently, the code uses the IH_VMID_X_LUT register to map a queue's vmid to the corresponding PASID. This logic is racy since CP can update the VMID-PASID mapping anytime especially when there are more processes than number of vmids. Update the logic to calculate CU occupancy by matching doorbell offset of the queue with valid wave counts against the process's queues. Signed-off-by: Mukul Joshi Reviewed-by: Harish Kasiviswanathan Signed-off-by: Alex Deucher

drm/amdkfd: support per-queue reset on gfx9

2024-08-06T14:43:18+00:00

Support per-queue reset for GFX9. The recommendation is for the driver to target reset the HW queue via a SPI MMIO register write. Since this requires pipe and HW queue info and MEC FW is limited to doorbell reports of hung queues after an unmap failure, scan the HW queue slots defined by SET_RESOURCES first to identify the user queue candidates to reset. Only signal reset events to processes that have had a queue reset. If queue reset fails, fall back to GPU reset. Signed-off-by: Jonathan Kim Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher

drm/amdkfd: Fix reg offset for setting CWSR grace period

2023-09-11T22:15:43+00:00

This patch fixes the case where the code currently passes absolute register address and not the reg offset, which HWS expects, when sending the PM4 packet to set/update CWSR grace period. Additionally, cleanup the signature of build_grace_period_packet_info function as it no longer needs the inst parameter. Signed-off-by: Mukul Joshi Reviewed-by: Jonathan Kim Signed-off-by: Alex Deucher

drm/amdkfd: add kfd2kgd debugger callbacks for GC v9.4.3

2023-07-12T14:58:01+00:00

Implement the similarities as GC v9.4.2, and the difference for GC v9.4.3 HW spec, i.e. xcc instance. Signed-off-by: Jonathan Kim Signed-off-by: Eric Huang Reviewed-by: Jonathan Kim Signed-off-by: Alex Deucher

drm/amdkfd: add debug set and clear address watch points operation

2023-06-09T16:36:46+00:00

Shader read, write and atomic memory operations can be alerted to the debugger as an address watch exception. Allow the debugger to pass in a watch point to a particular memory address per device. Note that there exists only 4 watch points per devices to date, so have the KFD keep track of what watch points are allocated or not. Signed-off-by: Jonathan Kim Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher

drm/amdkfd: add debug wave launch mode operation

2023-06-09T16:36:39+00:00

Allow the debugger to set wave behaviour on to either normally operate, halt at launch, trap on every instruction, terminate immediately or stall on allocation. Signed-off-by: Jonathan Kim Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher

drm/amdkfd: add debug wave launch override operation

2023-06-09T16:36:37+00:00

This operation allows the debugger to override the enabled HW exceptions on the device. On debug devices that only support the debugging of a single process, the HW exceptions are global and set through the SPI_GDBG_TRAP_MASK register. Because they are global, only address watch exceptions are allowed to be enabled. In other words, the debugger must preserve all non-address watch exception states in normal mode operation by barring a full replacement override or a non-address watch override request. For multi-process debugging, all HW exception overrides are per-VMID so all exceptions can be overridden or fully replaced. In order for the debugger to know what is permissible, returned the supported override mask back to the debugger along with the previously enable overrides. Signed-off-by: Jonathan Kim Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher