linux-next.git/Documentation/devicetree/bindings/memory-controllers, branch master

dt-bindings: fix typos and brackets

2026-08-07T14:38:47+00:00

Add missing '(', ')', '}' Remove needless '(', ')', '{', '}' 'lover voltage' -> 'lower voltage' Signed-off-by: Manuel Ebner Link: https://patch.msgid.link/20260722101246.3113818-2-manuelebnerli@mailbox.org [robh: drop .txt binding changes] Signed-off-by: Rob Herring (Arm)

Merge tag 'devicetree-for-7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux

2026-06-17T18:54:57+00:00

Pull devicetree updates from Rob Herring: "DT core: - Add support for handling multiple cells in "iommu-map" entries - Support only 1 entry in /reserved-memory "reg" entries. Support for more than 1 entry has been broken - Fix a UAF on alloc_reserved_mem_array() failure - Make "ibm,phandle" handling logic specific to PPC - Use memcpy() instead of strcpy() for known length strings - Ensure __of_find_n_match_cpu_property() handles malformed "reg" entries - Add various checks that expected strings are strings before accessing them - Drop redundant memset() when unflattening DT DT bindings: - Add a DTS style checker. Currently hooked up to dt_binding_check to check examples - Convert st,nomadik platform, ti,omap-dmm, and ti,irq-crossbar bindings to DT schema - Add Apple System Management Controller hwmon, Qualcomm Hamoa Embedded Controller, Qualcomm IPQ6018 PWM controller, fsl,mc1323, Samsung SOFEF01-M DDIC panel, Freescale i.MX53 Television Encoder, Samsung S2M series PMIC extcon, and MT6365 PMIC AuxADC schemas - Extend bindings for QCom Maili and Nord PDC, QCom Hali fastrpc, qcom,eliza-imem, qcom,oryon-1-5 CPU, and MT6365 Keys - Consolidate "sram" property definitions - Fix constraints on "nvmem" properties which only contain phandles and no arg cells - Another pass of fixing "phandle-array" constraints - Add Gira vendor prefix" * tag 'devicetree-for-7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (50 commits) dt-bindings: interrupt-controller: qcom,pdc: Add Maili compatible string dt-bindings: interrupt-controller: ti,irq-crossbar: Convert to DT schema dt-bindings: vendor-prefixes: add Gira dt-bindings: embedded-controller: Add Qualcomm reference device EC description dt-bindings: pwm: add IPQ6018 binding dt-bindings: hwmon: Add Apple System Management Controller hwmon schema docs: dt: writing-schema: Clarify what is required in a schema of: Respect #{iommu,msi}-cells in maps of: Factor arguments passed to of_map_id() into a struct of: Add convenience wrappers for of_map_id() of: reserved_mem: zero total_reserved_mem_cnt if no valid /reserved-memory entry of: reserved_mem: handle NULL name in of_reserved_mem_lookup() dt-bindings: cache: l2c2x0: Add missing power-domains dt-bindings: interrupt-controller: renesas,r9a09g077-icu: Fix reg size in example dt-bindings: nvmem: consumer: Make 'nvmem' an array of one-item entries drivers/of/overlay: Use memcpy() to copy known length strings dt-bindings: add self-test fixtures for style checker dt-bindings: wire style checker into dt_binding_check scripts/jobserver-exec: propagate child exit status dt-bindings: add DTS style checker ...

dt-bindings: memory: renesas,rzg3e-xspi: Add RZ/T2H and RZ/N2H support

2026-05-24T19:05:15+00:00

Document xSPI controller found on the Renesas RZ/T2H and RZ/N2H SoCs. The xSPI IP on these SoCs is identical to that found on the RZ/G3E SoC. The RZ/G3E HW manual (Rev.1.15) references bridge channel 1 and its bits, however the hardware actually supports only a single bridge channel (channel 0), matching the RZ/T2H design. The references to channel 1 and its configuration bits will be corrected in a future revision of the HW manual. Update clock/reset constraints to handle the SoC differences. Signed-off-by: Lad Prabhakar Reviewed-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260515115202.1515577-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Krzysztof Kozlowski

dt-bindings: drop tab characters from DTS examples

2026-05-05T15:54:45+00:00

YAML literal block scalars cannot use tabs for indent. Replace tab separators (mostly between values and trailing /* ... */ comments) with single spaces. Signed-off-by: Daniel Golle Reviewed-by: Krzysztof Kozlowski Link: https://patch.msgid.link/2044ee0cac191c7be8b6e989fc3c99b24aa4cc5e.1777434096.git.daniel@makrotopia.org Signed-off-by: Rob Herring (Arm)

Merge branch 'for-v7.2/tegra114-mc-bindings' into mem-ctrl-next

2026-05-04T18:46:50+00:00

dt-bindings: memory: Document Tegra114 External Memory Controller

2026-05-04T18:45:47+00:00

Include Tegra114 support into existing Tegra124 EMC schema with the most notable difference being the amount of EMC timings and a few SoC unique entries. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Rob Herring (Arm) Link: https://patch.msgid.link/20260427070312.81679-4-clamor95@gmail.com Signed-off-by: Krzysztof Kozlowski

dt-bindings: memory: Document Tegra114 Memory Controller

2026-05-04T18:45:46+00:00

Add Tegra114 support into existing Tegra124 MC schema with the most notable difference in the amount of EMEM timings. Each memory client has unique hardware ID, add these IDs. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Rob Herring (Arm) Link: https://patch.msgid.link/20260427070312.81679-2-clamor95@gmail.com Signed-off-by: Krzysztof Kozlowski

dt-bindings: memory: tegra: Add nvidia,tegra238-mc compatible

2026-05-04T17:26:49+00:00

Document the device tree binding for the Tegra238 memory controller. Tegra238 has 8 memory controller channels plus broadcast and stream-id registers. Add the stream ID header (nvidia,tegra238-mc.h) defining ISO and NISO stream IDs for SMMU configuration. Signed-off-by: Ashish Mhetre Reviewed-by: Jon Hunter Link: https://patch.msgid.link/20260427073419.567360-2-amhetre@nvidia.com Signed-off-by: Krzysztof Kozlowski

dt-bindings: memory: tegra210: Mark EMC as cooling device

2026-03-27T15:25:44+00:00

The external memory controller found on Tegra210 can use throttling of the EMC frequency in order to reduce the memory chip temperature. Mark the memory controller as a cooling device to take advantage of this functionality. Reviewed-by: Rob Herring Signed-off-by: Thierry Reding

dt-bindings: memory: Add Tegra210 memory controller bindings

2026-03-27T15:25:44+00:00

Document the bindings for the memory controller found on Tegra210 SoCs. Reviewed-by: Rob Herring (Arm) Signed-off-by: Thierry Reding